Abstract: An improved floating point unit is disclosed. The floating point unit includes a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand. The combined adder-shifter includes an adder portion that operates to generate a number of sum bits for exponent difference between the two floating point operands. The adder portion favors generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits. The combined adder-shifter also includes a shifter portion that operates to shift the mantissa portion of the at least one floating point operand in accordance with the sum bits.

Abstract: A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.

Abstract: A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each segment. Each segment undergoes all zeros detection, all ones detection, modified zeros detection, and modified ones detection. The modified zeros detection and modified ones detection are both done based on the control field. Each detection for each segment generates a response. Then, a pair of the four responses, or a clear responses signal, is selected for each of the segments based on the control field. From the selected responses, the method determines if the normalized data field is all zeros or all ones.

Abstract: A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first presumed carry-in signal and a second candidate carry-out signal is based on a second presumed carry-in signal different than the first presumed carry-in signal. A two-level selector for simultaneously selects, for each of the pairs of candidate carry-out signals, either the first candidate carry-out signal or the second candidate carry-out signal as an actual carry-out signal, based on an actual carry-in signal. Both selected carry out signals are passed to.

Abstract: A carry select adder includes an adder for outputting a first sum of values based on a first presumed carry-in of zero and a second sum of the values based on a second presumed carry-in of one. A sum unit produces an actual sum comprising either the first sum or the second sum based on an actual carry-in and simultaneously determines whether the actual sum is all zeros or all ones. The sum unit selects the actual sum and determines whether the actual sum comprises all zeros or ones in the same time period such that there is no significant additional delay associated with the zero/one detection operation.

Abstract: An apparatus and method for comparing values A comparator comprising inputting two comparison values to be compared, determining the number of a leading "1" in each of the values and outputting two position values, wherein the position values have a bit size smaller than the comparison values, comparing a first position value of the position values from a second position value of the position values, and outputting a signal indicating a first comparison value of the comparison values is either greater than a second comparison value of the comparison values, equal to the second comparison value or less than the comparison value, based on a result of the comparing operation.

Abstract: A fast 4-2 carry save adder using multiplexers and inverters only, for receiving four one bit data inputs and a one bit carry-in, and generating a sum and a carry-dependent output in three logic delays and a carry-independent carry out in two logic delays. The 4-2 carry adder has particular application in multiplier arrays.

Abstract: A high speed apparatus and method for determining the number of leading zeros or ones in a binary data field, in particular, a fixed-sized field, and further, indicating whether all of the bits of the binary data field are zero or one, is provided. The apparatus includes a plurality of detector circuits, coupled in parallel, to input different sections of the binary data field. For a leading zero detection operation, each detector circuit is configured to identify the bit location which contains the most significant "1" of the section of the binary data field which the detector inputs, and output a binary number signal representing the number of zeros leading that most significant "1". Each detector circuit also determines whether each bit location in the section which the detector inputs contains a "0" and provides a zero-detect signal representing this condition.

Abstract: A method and circuit for store rounding a number wherein the guard bit and least significant bit of the number are selectively exchanged depending on the IEEE rounding mode to simplify the decision-making circuit. Zero detection logic is performed on the guard, round and sticky bit positions to determine if incrementing is required. An incrementer provided with the number and a guard bit, which may be the true guard bit or a predetermined constant value depending on the rounding mode, responds to the zero detection logic to increment the number from the guard bit position.

Abstract: A structure for and method of operating a transition-controlled off-chip driver is disclosed. Turn-on of output pulling devices is controlled, while turn-off is uncontrolled. An AC voltage reference circuit dissipating essentially zero DC power provides a reference voltage for control during transition. Turn-on control dissipates during transition, and ends when transition is complete without the use of output feedback.

Abstract: A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of an M bit multiplicand and an N bit multiplier. The partial products generator outputs to the carry adder circuit partial products based on the M bit multiplicand and N bit multiplier. The carry adder circuit contains a plurality of carry adders connected in a hierarchical tree structure such that a plurality of carry adder stages are defined, with each carry adder stage except a first carry adder stage receiving adder sums from a next adjacent, lower carry adder stage in the hierarchical tree structure. The first carry adder stage receives the partial products output from the partial products generator. The multiplication circuit is optimized by employing carry select adders or carry look-ahead adders in the hierarchical tree structure.

Abstract: A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (T.sub.on) and low state (T.sub.off) intervals per cycle from a received clock signal having a substantially constant period but variable T.sub.on and T.sub.off intervals per cycle. The shaping network utilizes a set/reset latch to output the desired clock signal. The set input to the latch receives a set pulse generated at the beginning of each cycle of the received clock signal and the reset input to the latch receives a reset pulse generated by control logic circuitry. The logic circuitry uses the frequency of the received clock signal to generate a reset pulse at the appropriate time for gating of the latch to produce an output clock signal having the desired T.sub.on and T.sub.off intervals per cycle.

Abstract: A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Abstract: A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (T.sub.on) and low state (T.sub.off) intervals per cycle from a received clock signal having a substantially constant period but variable T.sub.on and T.sub.off intervals per cycle. The shaping network utilizes a set/reset latch to output the desired clock signal. The set input to the latch receives a set pulse generated at the beginning of each cycle of the received clock signal and the reset input to the latch receives a reset pulse generated by control logic circuitry. The logic circuitry uses the frequency of the received clock signal to generate a reset pulse at the appropriate time for gating of the latch to produce an output clock signal having the desired T.sub.on and T.sub.off intervals per cycle.

Abstract: A logic synthesis network for efficiently combining respective bit pairs of first and second operands to produce respective sum bits and a carry bit associated with the most significant sum bit. A dummy generator receives the respective bit pairs and generates first and second dummy sum signals, and first and second pairs of dummy carry signals. A first dummy selector chain selects the appropriate dummy sum and carry signals of all the bits other than the least significant bit, as a function of the state of the first pair of dummy carry signals generated for the least significant bit pair. A second dummy select chain selects the appropriate dummy sum and carry signals for all the bit pairs other than the least significant bit pair, as a function of the state of the second pair of dummy carry signals generated for the least significant bit pair.

Abstract: A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors and first and second N-channel field effect transistors, a first data signal is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse, i.e.

Abstract: Digital binary multipliers are provided which include first and second inverting full adders, each having first, second and third input terminals and first and second output terminals, the first output terminal of the first adder being connected to the first input terminal of the second adder with the first, second and third input terminals and the first and second output terminals of the second adder having a relationship with respect to the input and output terminals of the first adder such that corresponding input and output terminals have opposite signal polarities or complementary terminals, i.e., when one of these input or output terminals of the first adder has a true polarity signal, its corresponding input or output terminal of the second adder has a complemented polarity signal.

Abstract: An inverting full adder circuit for use in a ripple-carry adder or arithmetic logic unit (ALU) which includes a plurality of similar full adder stages connected in series such that the carry delay from one stage to the next is minimized, and which requires fewer devices and less space on the surface of a semiconductor chip than do known adders or ALUs of comparable performance. This invention may use either N-channel field effect transistors, i.e., NMOS technology, or it may use complementary metal oxide semiconductor (CMOS) technology.

Abstract: A layout for random logic in which different stages are assigned to columns according to the flow of logic signal. Each stage may consist of several parallel logic blocks defining a logic function and having an output. The logic blocks are implemented by several diffusion areas, not necessarily contiguous. The output line of a logic block is aligned vertically to match one or more gate electrodes of following stages that it drives. The interconnection to the following stages can be implemented by a single horizontal polysilicon line which also functions as the gate electrodes. The breaks in the diffusion of a logic block can accommodate the passage of polysilicon lines not being used in that logic block.