Abstract: Examples of circuitry and systems and methods provide a multi-way configurable amplifier to support various applications. The multi-way configurable amplifier may include a reconfigurable filter that comprises first and second inputs adapted to receive an input signal; a fully differential amplifier (FDA); and first and second reconfigurable resistance-capacitance (RC) networks. The FDA has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the first input, and the non-inverting input is coupled to the second input. The first reconfigurable RC network is coupled to the non-inverting output, and the second reconfigurable RC network is selectively couplable to the inverting output. The reconfigurable filter is configurable to enable operation in any of multiple modes including a single-ended mode of operation and a differential mode of operation.

Abstract: In an example, a dual-phase inverting buck-boost power converter for use with at least first and second energy storage elements includes an inverting buck-boost power converter and an inverting boost converter. In an example, the inverting buck-boost power converter is coupled between an input node and an output node of the dual-phase inverting buck-boost power converter and includes a first plurality of switches operable to couple to the first energy storage element, wherein the inverting buck-boost power converter is operable to supply a first load current. In an example, the inverting boost converter is coupled in parallel with the inverting buck-boost power converter between the input node and the output node of the dual-phase inverting buck-boost power converter and includes a second plurality of switches operable to couple to the first and the second energy storage elements, wherein the inverting boost converter is operable to supply a second load current.

Abstract: In an example, a dual-phase inverting buck-boost power converter for use with at least first and second energy storage elements includes an inverting buck-boost power converter and an inverting boost converter. In an example, the inverting buck-boost power converter is coupled between an input node and an output node of the dual-phase inverting buck-boost power converter and includes a first plurality of switches operable to couple to the first energy storage element, wherein the inverting buck-boost power converter is operable to supply a first load current. In an example, the inverting boost converter is coupled in parallel with the inverting buck-boost power converter between the input node and the output node of the dual-phase inverting buck-boost power converter and includes a second plurality of switches operable to couple to the first and the second energy storage elements, wherein the inverting boost converter is operable to supply a second load current.

Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.

Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.