Abstract: A precision delay circuit in an integrated circuit chip includes a transistor switching circuit in combination with a control circuit and a compensation circuit. The transistor switching circuit receives an input signal; and in response, the transistors switch on and off at an unpredictable speed to generate an output signal with a delay that has a large tolerance. The control circuit estimates the unpredictable speed at which the transistors switch and it generates control signals that identify the estimated speed. The compensation circuit includes a plurality of compensation components for the transistor switching circuit. This compensation circuit receives the control signals from the control circuit; and in response, it selectively couples the compensation components to the transistor switching circuit such that the combination of the transistors and the selectively coupled components generates the output signal with a precise delay that has an insignificant tolerance.

Abstract: In one method according to the present invention, an integrated circuit chip is fabricated by the following steps:1) providing a trial layout in the chip for a victim net and a set of aggressor nets which have segments that lie next to the victim net;2) assigning to the trial layout of the victim net, the parameters of--a line capacitance, a line resistance, and a driver output resistance; and assigning to the trial layout of each aggressor net, the parameters of--a coupling capacitance to the victim net, and a voltage transition;3) estimating, for each aggressor net, a respective peak crosstalk voltage V.sub.p which the aggressor net couples into the victim net as a function V.sub.p =K(e.sup.-X -e.sup.

Abstract: A memory in an integrated circuit chip includes an array of memory cells and a read/write circuit which performs precharge and sense operations on the array for a time interval that is set by the width of a pulse signal. This pulse signal is generated by a pulse generator circuit which contains transistors that switch on and off at an unpredictable speed; and consequently, the width of the pulse signal has a large tolerance. To decrease this large tolerance in the pulse signal, a compensation circuit is provided which includes a plurality of compensation components for the pulse generator. This compensation circuit selectively couples the compensation components to the pulse generator such that the selectively coupled components in combination with the pulse generator's transistors produce the pulse signal with a precise width that has an insignificant tolerance.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the present invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of an equation.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the preset invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of a table.

Abstract: An integrated circuit die contains a total of at least 10,000 bipolar logica cells that dissipate at least 75 watts of power. To supply such a large amount of power to the logic cells, thin sputtered power busses of 3 .mu.m thickness overlie the logic cells; an insulating layer surrounds the power busses; openings in the insulating layer defined plating regions on the power busses; an electroplating base film lies throughout the plating regions; and, a thick plated conductor, of at least 16 .mu.m thickness, lies on the electroplating base film. By supplying power to the bipolar logic cells via the composite structure of the thin power busses and thick plated conductors, a noise margin problem in the logic cell output signals is avoided. With 16 .mu.m thick plated conductors, the total number of logic cells on the die can be increased until their total power dissipation reaches 75 watts. With 21 .mu.m thick plated conductors, total die power can be increased to 100 watts.

Abstract: Additional logical structures are respectively interactive with either an edge-triggered dual D-type flip-flop or an edge-triggered J-K flip-flop in order that each such flip-flop may be fully scan-set testable in all the elements thereof. Two scan-set test enabling signals, as well as two scan-set clock signal, are used to conduct three tests, as well as enabling normal edge-triggered operation. The three tests enable scan-set testability of the totality of the edge-triggered flip-flop. Two of the tests characteristically cause the logical interconnection of tested logical elements as inverter strings, which inverter strings are merged into the scan-set test loops. In addition to supporting functional logical verification, the inverter strings support the evaluation of propagation time upon such strings in order to determine the operational speed and/or impedance environment of the tested flip-flops. Marginal, as well as failed, flip-flops (flip-flop environments) are identifiable.

Abstract: Apparatus for correcting memory errors by testing the addressable location causing the memory error in realtime. The memory responds to read requests by accessing the contents of the requested addressable location. If the contents of the addressable location contain errors, which are uncorrectable by other means, the memory saves the erroneous data word and the requested addressable location is tested by immediately writing into and reading from the requested addressable location. Two data words are sequentially written into and read from the requested addressable location which cause both a one and a zero to be written into each bit position of the requested addressable location. If the reads reveal an error at any bit positions of the requested addressable location, the corresponding bit positions of the erroneous data word are complimented and the resultant is transferred to the requestor using the normal data path.