Patents by Inventor Roland G. de Jonge

Roland G. de Jonge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8976497
    Abstract: An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating device with an input terminal coupled to the interface output. By floating the device receiving the ESD event in the second power domain, damaging ESD induced voltages are reduced. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Synopsys, Inc.
    Inventors: Robert B. Lefferts, Peter C. de Jong, Roland G. de Jonge
  • Patent number: 8958186
    Abstract: An electrostatic discharge (ESD) device is implemented within a power domain to mitigate imparting ESD induced voltages on other power domains for reducing integrated circuit (IC) failures. A first power domain includes an interface with a first terminal where an ESD event is received. The interface includes a second terminal coupled to a component within a second power domain. The ESD device is disposed between the first terminal and second terminal to intercept the ESD event. In one embodiment, the ESD device includes a blocking device. The blocking device operatively decouples the first terminal and second terminal in response to a trigger signal received during an ESD event. By operatively decoupling the terminals, transmission of the ESD induced voltages is substantially mitigated. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: February 17, 2015
    Assignee: Synopsys, Inc.
    Inventors: Robert B. Lefferts, Peter C. de Jong, Roland G. de Jonge
  • Publication number: 20140092507
    Abstract: An electrostatic discharge (ESD) device is implemented within a power domain to mitigate imparting ESD induced voltages on other power domains for reducing integrated circuit (IC) failures. A first power domain includes an interface with a first terminal where an ESD event is received. The interface includes a second terminal coupled to a component within a second power domain. The ESD device is disposed between the first terminal and second terminal to intercept the ESD event. In one embodiment, the ESD device includes a blocking device. The blocking device operatively decouples the first terminal and second terminal in response to a trigger signal received during an ESD event. By operatively decoupling the terminals, transmission of the ESD induced voltages is substantially mitigated. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Applicant: SYNOPSYS, INC.
    Inventors: Robert B. Lefferts, Peter C. de Jong, Roland G. de Jonge
  • Publication number: 20130314824
    Abstract: An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating device with an input terminal coupled to the interface output. By floating the device receiving the ESD event in the second power domain, damaging ESD induced voltages are reduced. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: Synopsys, Inc.
    Inventors: Robert B. Lefferts, Peter C. de Jong, Roland G. de Jonge