Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.

Abstract: In certain embodiments, a bond gap control structure (BGCS) is placed outwardly from a substrate. The BGCS is configured to control a geometry of a bond line of a joining material. The joining material is deposited outwardly from the substrate. The substrate is bonded to another substrate with the joining material. The BGCS is at least partially removed from the substrate.

Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A wafer level vacuum packaged (WLVP) device having a first substrate having an array of detectors and a second substrate bonded to the first substrate having a plurality of protrusions and a plurality of getter material members projecting outwardly from a sidewall of the protrusions members are disposed at oblique angles to the sidewalls and have ends extending into gaps between the protrusions. The device is formed by: forming protrusions into a surface of a substrate; and depositing getter material by physical vapor deposition from an evaporating source of the getter material at an oblique angle to the sidewalls, atoms of the getter material initially forming nucleation sites on the sidewalls with subsequent atoms attaching to the nucleation sites and shadowing area surrounding each nucleation site, the getter material thereby growing into structures towards the evaporating source.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: In certain embodiments, a bond gap control structure (BGCS) is placed outwardly from a substrate. The BGCS is configured to control a geometry of a bond line of a joining material. The joining material is deposited outwardly from the substrate. The substrate is bonded to another substrate with the joining material. The BGCS is at least partially removed from the substrate.

Abstract: Methods for making optically blind reference pixels and systems employing the same. The reference pixels may be configured to be identical to, or substantially identical to, the active detector elements of a focal plane array assembly. The reference pixels may be configured to use the same relatively longer thermal isolation legs as the active detector pixels of the focal plane, thus eliminating joule heating differences. An optically blocking structure may be placed in close proximity directly over the reference pixels.

Abstract: Systems and methods for solder bonding that employ an equilibrium solidification process in which the solder is solidified by dissolving and alloying metals that raise the melting point temperature of the solder. Two or more structure surfaces may be solder bonded, for example, by employing heating to melt the solder and holding the couple at a temperature above the initial solder melting point of the solder until interdiffusion reduces the volume fraction of liquid so as to form a solid bond between surfaces before cooling to below the initial melting point of the solder.

Abstract: Methods for making optically blind reference pixels and systems employing the same. The reference pixels may be configured to be identical to, or substantially identical to, the active detector elements of a focal plane array assembly. The reference pixels may be configured to use the same relatively longer thermal isolation legs as the active detector pixels of the focal plane, thus eliminating joule heating differences. An optically blocking structure may be placed in close proximity directly over the reference pixels.

Abstract: A method for manufacturing optically-transparent lids includes etching sub-wavelength structures on a surface of a lid wafer. The structures may be arrayed in a hexagonally closed-packed pattern.

Abstract: A method for manufacturing integrated circuit device lids includes creating a lid cavity on the surface of a lid wafer, forming a sealing surface on the lid wafer that surrounds the lid cavity, and forming a trench on the lid wafer between the lid cavity and the sealing surface. The resulting structure uptakes excess sealing surface material and prevents such material from entering the lid cavity.