Abstract: A pulse generation and sensing arrangement in a microprocessor system (100) includes an input/output terminal (130) which receives an input signal or produces an output signal, an edge detector (132) which senses pulse edges in the input signal, timers (108, 110) which produce time values, registers (120, 124, 126) which hold time values produced by the timers corresponding to edges detected by the edge detector or which hold values corresponding to pulse edges to be generated, comparators which compare the values held in the registers with time values produced by the timers, and a flip-flop (128) for generating a signal whose state changes in response to the comparators. The arrangement allows the generation and/or sensing of signals with short pulse widths and a wide range of duty cycles, and minimizes software overhead. A continuous PWM signal may be generated without further software involvement after initial writing of edge values.

Abstract: A bus system has a main bus and an internal bus. The main bus is coupled to a number of driver units which drive data onto the main bus and to receiver units which respond to that data and provide response data to the main bus. A logic unit provides two-way communication directly between the main and internal buses and allows testing of individual driver and receiver units independently of other units.

Abstract: A memory system, having security against unauthorized accessing of the contents of the memory system, comprises a first alterable memory (6), a second non-alterable memory (14, 16) and a data bus (5) for allowing external access to data stored in the memory system during a test mode of operation. The first alterable memory (6) comprises an options register (10) having a security bit (SEC) which, when programmed to an active state, prevents external access to the data stored in the first alterable memory during the test mode. The first alterable memory (6) further comprises a first data memory (8) having at least one security byte (VALSEC) which, when programmed to a predetermined state, prevents external access to the data stored in both the first alterable memory (6) and the second non-alterable memory (14, 16) during the test mode.