Patents by Inventor Roland J. Awusie
Roland J. Awusie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11749373Abstract: A first pool of blocks of a memory device is determined, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell. A second pool of blocks of the memory device is determined, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell. In response to detecting a failure associated with a particular block of the second pool of blocks, the particular block is added to the first pool of blocks.Type: GrantFiled: April 28, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventor: Roland J. Awusie
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Publication number: 20220254436Abstract: A first pool of blocks of a memory device is determined, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell. A second pool of blocks of the memory device is determined, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell. In response to detecting a failure associated with a particular block of the second pool of blocks, the particular block is added to the first pool of blocks.Type: ApplicationFiled: April 28, 2022Publication date: August 11, 2022Inventor: Roland J. Awusie
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Patent number: 11367502Abstract: A processing device in a memory system performs operations comprising determining a first pool of data blocks of the memory device, wherein data blocks of the first pool are associated with storing data at a first number of bits per memory cell; determining a second pool of data blocks of the memory device, wherein data blocks of the second pool are associated with storing data at a second number of bits per memory cell that is larger than the first number of bits per memory cell; detecting a failure associated with a particular data block of the second pool of data blocks; and in response to detecting the failure associated with the particular data block, removing the particular data block from the second pool of data blocks and adding the particular data block to the first pool of data blocks.Type: GrantFiled: July 9, 2020Date of Patent: June 21, 2022Assignee: Micron Technology, IncInventor: Roland J. Awusie
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Publication number: 20200342949Abstract: A processing device in a memory system performs operations comprising determining a first pool of data blocks of the memory device, wherein data blocks of the first pool are associated with storing data at a first number of bits per memory cell; determining a second pool of data blocks of the memory device, wherein data blocks of the second pool are associated with storing data at a second number of bits per memory cell that is larger than the first number of bits per memory cell; detecting a failure associated with a particular data block of the second pool of data blocks; and in response to detecting the failure associated with the particular data block, removing the particular data block from the second pool of data blocks and adding the particular data block to the first pool of data blocks.Type: ApplicationFiled: July 9, 2020Publication date: October 29, 2020Inventor: Roland J. Awusie
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Patent number: 10770156Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.Type: GrantFiled: May 18, 2019Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
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Patent number: 10726936Abstract: A first group of data blocks of a memory sub-system is determined. The first group of data blocks is associated with a failure condition. Also, a second group of data blocks of the memory sub-system is determined. The second group of data blocks is not associated with the failure condition. User data is received and system data of the memory sub-system that is associated with the user data is generated. The system data is stored at the first group of data blocks that is associated with the failure condition by using a first programming operation. The user data is stored at the second group of data blocks that is not associated with the failure condition by using a second programming operation. The second programming operation is different from the first programming operation.Type: GrantFiled: December 20, 2018Date of Patent: July 28, 2020Assignee: MICRON TECHNOLOGY, INC.Inventor: Roland J. Awusie
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Publication number: 20200202970Abstract: A first group of data blocks of a memory sub-system is determined. The first group of data blocks is associated with a failure condition. Also, a second group of data blocks of the memory sub-system is determined. The second group of data blocks is not associated with the failure condition. User data is received and system data of the memory sub-system that is associated with the user data is generated. The system data is stored at the first group of data blocks that is associated with the failure condition by using a first programming operation. The user data is stored at the second group of data blocks that is not associated with the failure condition by using a second programming operation. The second programming operation is different from the first programming operation.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventor: Roland J. Awusie
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Patent number: 10510422Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: GrantFiled: September 10, 2018Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
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Publication number: 20190272881Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.Type: ApplicationFiled: May 18, 2019Publication date: September 5, 2019Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
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Patent number: 10340016Abstract: A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.Type: GrantFiled: June 26, 2017Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
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Publication number: 20190043592Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: ApplicationFiled: September 10, 2018Publication date: February 7, 2019Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
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Publication number: 20190043590Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: ApplicationFiled: August 4, 2017Publication date: February 7, 2019Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
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Patent number: 10199111Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: GrantFiled: August 4, 2017Date of Patent: February 5, 2019Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
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Publication number: 20180374549Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi