Abstract: An acquisition unit of a GNSS receiver base band circuit comprises a correlator (40) with a correlator shift register (43) to which a correlation sequence derived from a basic sequence characteristic for a satellite is fed by a code generator (41). Each of the N=32 or more memory cells of the correlator shift register (43) is connected to two correlator cells (44a, 44b) for multiplying digital values of the correlator sequence from the memory cell with data values of a data sequence, adding up the products and storing the sum in a register as a correlation value pertaining to one of N relative phase positions of the correlation sequence relative to the data sequence during a correlation phase.

Abstract: An acquisition unit of a GNSS receiver base band circuit comprises a correlator (40) with a correlator shift register (43) to which a correlation sequence derived from a basic sequence characteristic for a satellite is fed by a code generator (41). Each of the N=32 or more memory cells of the correlator shift register (43) is connected to two correlator cells (44a, 44b) for multiplying digital values of the correlator sequence from the memory cell with data values of a data sequence, adding up the products and storing the sum in a register as a correlation value pertaining to one of N relative phase positions of the correlation sequence relative to the data sequence during a correlation phase.

Abstract: A method of and a circuit arrangement for decoding RS-coded data signals is which data signals may be coded both in accordance with a code generator polynomialG(x)=(x+.alpha..sup.0) (x+.alpha..sup.1) . . . (x+.alpha..sup.15)and in accordance with a code generator polynomialG(x)=(x+.alpha..sup.120)(x+.alpha..sup.121) . . . (x+.alpha..sup.135).Dependent on the relevant code generator polynomial, switching takes place between two different constant multipliers in syndrome generators, and syndromes and erasure locations which have been determined are subjected to a Euclid's algorithm for deriving error location polynomials and error value polynomials. Error locations and error values for a code generator polynomial starting with .alpha..sup.0 are computed by means of a Chien zero search. Parallel thereto, a correction factor for a code generator polynomial starting with .alpha..sup.120 is determined. The computed error values of the code generator polynomial starting with .alpha..sup.

Abstract: Circuitry for detecting and correcting errors in data words occurring in Reed-Solomon coded blocks contains a plurality of stages. One stage constructs syndromes in the data flowing through the blocks. Another stage detects erasures in the syndromes. Another stage applies a Euclid's algorithm withT.sub.s (x)={Q.sub.s-1 (x).multidot.T.sub.s-1 (x)}+T.sub.s-2 (x),R.sub.s (x)={Q.sub.s-1 (x).multidot.R.sub.s-1 (x)}+R.sub.s-2 (x),andI Q.sub.s-1 (x)=R.sub.s-2 (x)/R.sub.s-1 (x)wherein T.sub.s (x), R.sub.s (x), and Q.sub.s-1 (x) are polynomials representing the position of the error, its value, and a provisional value respectively, and R.sub.s (x) and T.sub.s (x) can be normalized with a minimal coefficient T.sub.s (0)=.delta. such that R(x)=R.sub.s (xi/.delta. and T(x)=T.sub.s (x)/.delta.. Another stage detects error positions X.sub.k and values Y.sub.k by conducting a Chien zero-root search in conjunction with ##EQU1## wherein T'(X.sub.k) is the first derivative of T at a place x.sub.k.

Abstract: As many as three of the four heads spaced at 90.degree. intervals around the periphery of a head wheel may be in contact with the magnetic tape of a video recorder and reproducer at the same time. Oblique tracks are recorded on the tape record video date in blocks corresponding to sectors, each composed of the same numbers of lines, each track beginning with a video sector and ending with another video sector with small audio blocks inbetween. Four different sector designations succeed each other in turn. The video data of each block is preceded by an identification signal of which the two most significant bits designate the sector. The sector designations are separated from the outputs of each of the magnetic heads and control a PROM, the output of which controls a crosspoint switch to direct data blocks in accordance with the sector identification to four memories and the audio blocks to an audio memory.

Abstract: For reliable playback of digital video signals in slow-motion operation over a wide range of slow-motion speeds, auxiliary playback heads are positioned closely behind normal playback heads and offset by half a track width therefrom. Each of the playback heads have a circuit for regenerating clock and data signals which includes a PLL circuit and all of the PLL circuits have an output for the signal that shows whether the PLL circuit is locked in or not. The lock-in signals are supplied to first address inputs of an ROM which has a principal output showing whether the normal playback heads or the auxiliary playback heads have the larger number of locked-in PLL circuits and the group of playback heads having that larger number of locked-in PLL circuits is selected for having the data and clock signal outputs passed on to playback channels for further processing. The control of the switching circuit is improved by having auxiliary outputs of the ROM fed back to second address inputs thereof.

Abstract: A magnetic tape recorder/reproducer for digital video signals has an error recognition circuit unit as well as circuit units for correction and/or concealment of recognized errors in the video signal. During a tracking adjustment procedure a manual control added to the tracking adjuster reduces the capability of error correction and/or concealment by black-marking erroneous words recognized in the luminance portion of the digital video signal.

Abstract: In the detection and correction of errors in the decoding of data words of a series of data word blocks each provided with check words in accordance with a Reed-Solomon code the results of the necessary calculations are precomputed and stored in permanent memory addressable by the corresponding values of syndromes and position designating numbers. In the real time correction of detection errors the predetermined correction result is obtained from the ROM in response to the generated addresses and is then exclusive-OR correlated with the corresponding data words which have been delayed by one block interval in order to correct a correctable error. The amount of ROM storage can be reduced by the use of two ROMs and several registers. Error flags for uncorrectable errors are also passed on to succeeding circuits.

Abstract: The active portion of every television line of a digital video signal is used to generate checked data according to a Reed-Solomon block code, line-sequentially with the data of the digital video signal. The Reed-Solomon check data are then added in the horizontal blanking intervals of the digital video signal for error detection and correction processing, so that there is no necessity to provide additional memory circuits in parallel to the memory used to store temporarily the video data of the active portion of television lines. The semiconductor memory distributes the digital video signal data of the active portion of each line by cyclically allocating the data words thereof to n data word planes to form a data block. A Reed-Solomon coder is provided for each plane of the memory and likewise a Reed-Solomon decoder for the read-out of each plane, the check data for each plane being stored in their respective planes during the blanking interval following the active line.

Abstract: A PROM has inupts from error detecting and processing equipment of the signal reproducing channels of equipment reproducing digital signals from magnetic tape and can be controlled to process selectively the recognition of errors and of their respective natures by the error detecting and correcting circuits. The error detection circuits also provide a block end signal at the end of every block of data of the digital signal being processed which is protected against errors by check words. At every block end signal the output of the PROM is transferred to a first register, the contents of which are made available to an adder for adding these contents to the contents of the second register (10) and the output of the adder is written into the second register, either without change or after division by two by a switch (12), to the output of the second register.

Abstract: Data blocks recorded on oblique tracks on magnetic tape are preceded by synhronizing signals and block identification signals. The serial data identification signals are converted to 8-bit parallel form and then are split between an undelayed channel and a channel delayed by one data block. Under control of a sync detector the parallel data are made to correspond with data words and are then decoded for comparison of the block numbers. Since the block numbering is consecutive, the delayed decoded block number is incremented by one for comparison. When a positive comparison is obtained the block number of the delayed decoded signals is made available to identify the data block. A counter in a so called fly wheel circuit assures provision of a new block start signal if a synchronizing signal is missed and prevents the timing of the circuit from being put off by a false detection of a synchronizing signal. A block identification output appears only if its block number is in sequence.

Abstract: Test node equipment is provided between successive component groups operating in cascade and each test node is connected to a data bus system through which test patterns can be provided by a test pattern generator and from which signals can be evaluated by a test pattern analyzer, the test pattern generator and the test pattern analyzer being under control of a test computer. Each test node has a state in which the output of the preceding component group passes through it to the next component group with only a possibility of monitoring possible deficiencies by the test computer and other states in which the cascade operation of component groups can be interrupted at a test node for inserting a test pattern to a following component group or receiving a processed test pattern from a preceding component group.

Abstract: 8-bit data words and check words of a data block are supplied to an error recognition circuit the same time that they are written into a FIFO storage unit a word clock rate derived from the signals reproduced from a magnetic tape record which are subject to phase fluctuations. At the same time a counter is advanced by the same clock pulses. The error recognition circuit forms syndrome words by which each erroneous data word can be located and its address stored, as the state of the counter, into a register which is capable of registering more than one such address. The error recognition circuit also generates an error pattern multibit signal which is likewise stored in a register which can store more than one error pattern.

Abstract: A system for testing and/or monitoring a digital videotape apparatus makes use of the presence several identically equipped recording and reproducing channels to detect or test for errors by comparing the treatment of the same data in two or more channels. Comparisons are made at test nodes between reference "signatures" and actual "signatures" in normal operation or in test operation. Syndrome units are used to test or monitor circuits for protection against errors and for error correction. The monitoring and testing is done in a system which connects a microcomputer to test nodes of the equipment to be tested or monitored over a test bus.

Abstract: Four picture field memories which contain storage places for luminance data, chrominance data, error flags and write flags are switchable from write in to read out by changeover switches controlled by an access control unit for connection of the address and control inputs of the memories either to a write in control circuit or a read out control circuit. The access control unit can be set for operation at normal speed, which is the recording speed of the tape from which signals are read out, below normal speed or above normal speed. The read-out control circuit is synchronized by a synchronizing signal that contains a vertical scan frequency reference pulse. The several picture field memories are cyclically interchanged, written into and read out from. One of the picture field memories is read out while the others are available for write-in. The incoming error flags are passed on. Use is made of write flags and error flags to improve operation at speeds different from the recording speed.

Abstract: In a magnetic tape machine which can be played to reproduce television pictures at speeds different from the recording speed, in connection with which the video signals are stored in a picture memory, the video signals are stored under group addresses in 60-byte blocks, both for the luminance and chrominance signals. After a predetermined storage period has elapsed, the stored data are overwritten with erasing value signals. A circuit arrangement for this operation includes an administrative memory (4) for which the storage duration values for contents stored under every block address is, beginning after writing-in, successively reduced in value. When a zero value is reached, the corresponding block address is stored and used in its turn as a write-in address for the erasing value signals which replace the video data previously written in to the picture memory under this address.

Abstract: Digital color television signals intended to be recorded in serial bit form are first subjected to predistortion to compensate for nonlinear distortion digitally computed for each serial bit on the basis of the pattern established by a predetermined number of precursor bits, which requires digital to analog conversion of the multibit parallel output of the predistortion computation. The converted output is then filtered on an analog basis to compensate for linear distortion, as by emphasizing the higher frequencies. In reproduction, the similar combination of analog and digital distortion compensation is used, first filtering and then, after retrieving the bit clocking frequency and phase, analog to digital conversion and compensation for nonlinear distortion by programmed interpretation of a parallel multibit input to select correctly the bits of an output serial bit stream. The latter can be subjected to conversion into the usual eight bit parallel color television signals.