Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

Abstract: In examples, a voltage-controlled oscillator (VCO) comprises an inductor; a first pair of transistors having first terminals coupled to a voltage source, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor; and a second pair of transistors having first terminals coupled to ground, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor. The VCO also comprises a first transistor coupled to at least one capacitor, the combination of the first transistor and the at least one capacitor coupled to the inductor in parallel. The VCO further comprises second, third, and fourth transistors coupled to a control terminal of the first transistor, the second transistor coupled to the voltage source, the fourth transistor coupled to ground, and the third transistor configured to receive a ramped voltage.

Abstract: In examples, a voltage-controlled oscillator (VCO) comprises an inductor; a first pair of transistors having first terminals coupled to a voltage source, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor; and a second pair of transistors having first terminals coupled to ground, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor. The VCO also comprises a first transistor coupled to at least one capacitor, the combination of the first transistor and the at least one capacitor coupled to the inductor in parallel. The VCO further comprises second, third, and fourth transistors coupled to a control terminal of the first transistor, the second transistor coupled to the voltage source, the fourth transistor coupled to ground, and the third transistor configured to receive a ramped voltage.