Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Abstract: The invention provides an initialization routine for digital signal processors that detects and maps out soft errors. A digital signal processing system may include an initialization routine stored in a non-volatile memory device that writes a bit pattern to the memory arrays. The routine may then cause the processor to perform refresh cycles to refresh the charge of each bit in the arrays. Next, the initialization routine may read data values from the memory arrays and compare them with the previously written bit pattern. If a value does not match the bit pattern, then the bit may have failed due to a soft error. An indication of the failed bit may then be stored in the first few rows of the memory array, thereby mapping out the failed location.

Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Abstract: An integrated circuit (IC) module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Multi-Chip Module (MCM), includes a buffering IC that buffers clock and other input signals received by the IC module. As a result of the buffering, the setup and hold times associated with these input signals are improved, thereby improving yields.

Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Abstract: With the present invention, a component may be identified based upon selected physical characteristics of the component. In one embodiment, a system is provided for storing information pertaining to components within a set of components. A characterization function, which is a function of relevant physical characteristics shared by each component within the set of components, is associated with the set of components. The system includes a characterization value test station and a database. The characterization value test station is used to determine the characterization values of the components pursuant to the characterization function. The database stores information that pertains to each component with the component's characterization value linked as an identifier to the information. In this manner, information pertaining to a component may be retrieved from the database based on the component's characterization value.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: The present invention provides a method for identifying components based upon selected physical characteristics. Initially, a characterization function that will produce a unique characterization value within a set of components, is (or has been) assigned to the set of components. The characterization function is a function of at least one physical characteristic that is shared by the components within the set of components. Next, the measurable physical characteristics defined as part of the characterization function are measured by testing. A characterization value, which is calculated from the assigned characterization function, is determined for each component. Each component that is to be subsequently identified is then identified by its associated characterization value.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A system and method for assembling components onto a circuit board is disclosed. The system includes: a thermal chamber for receiving a plurality of components therein and for heating the plurality of components at a predetermined temperature for a predetermined length of time; an outfeed slot located on a wall of the thermal chamber which allows at least one component from the plurality of components to pass therethrough and emerge externally of the thermal chamber; and a pick and place machine, located adjacent to the thermal chamber, which automatically retrieves the at least one component which has passed through the outfeed slot and automatically places the at least one component onto a designated circuit board.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuts includes two devices(40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier(14) with a second current level, different from the first current level. The selector (14) is couple to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices(40and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Abstract: An apparatus, system and method for identifying an access mode of a semiconductor memory in a data processing system, characterized by significant reduction of the possibility of erroneous identification of the access mode. A semiconductor memory has an access circuit bank with plurality of selectable circuits only one of which is activated, each selectable circuit respectively associated with a selectable semiconductor memory access mode, the access mode selection typically being accomplished by selectively blowing fuses associated with the corresponding selectable circuits. A semiconductor memory access mode is correctly identified by associating, in response to a test signal for determining the fuse status, the respective activated selectable circuit with its corresponding access mode.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: To permit effective testing of a sense amplifier circuit, the sense amplifier is designed to be responsive to data stored in a selected memory cell in a controlled test mode. The sense amplifier circuit includes a pull-down circuit having delay circuit to receive and respond to a control signal which indicates whether the sensing circuit is to operate in test mode or normal mode. The sense amplifier circuit also includes an output circuit which is configured and arranged to generate a reference signal corresponding to the data stored in a selected memory cell. To permit sufficient time to test the circuit for correct data values at the output signal, the reference signal is delayed in response to the control signal indicating that the sensing circuit is to operate in test mode.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: To permit effective testing of a sense amplifier circuit, the sense amplifier is designed to be responsive to data stored in a selected memory cell in a controlled test mode. The sense amplifier circuit includes a pull-down circuit having delay circuit to receive and respond to a control signal which indicates whether the sensing circuit is to operate in test mode or normal mode. The sense amplifier circuit also includes an output circuit which is configured and arranged to generate a reference signal corresponding to the data stored in a selected memory cell. To permit sufficient time to test the circuit for correct data values at the output signal, the reference signal is delayed in response to the control signal indicating that the sensing circuit is to operate in test mode.