Abstract: A differential bus having a controllable differential signal development rate. A differential signal development rate control circuit is provided to control the development rate of a differential signal on a differential bus.

Abstract: A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the virtual address which are untranslated between the virtual address and the physical address. The partial physical address is used to identify a block of the cache index sets that might contain an address of requested data. The identification is performed prior to translation of the virtual address to the physical address. Once identified, the block is read out into an auxiliary memory structure. After the full physical address becomes available, the block is multiplexed down to one set, and a compare is performed on the ways of the set to determine if the requested data is in the cache and, if so, which way the data is in. A device for achieving the method includes a cache index organized into two arrays, each having a number of sets and a number of ways. One of the arrays may used to store micro-tags for way prediction.

Abstract: A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the virtual address which are untranslated between the virtual address and the physical address. The partial physical address is used to identify a block of the cache index sets that might contain an address of requested data. The identification is performed prior to translation of the virtual address to the physical address. Once identified, the block is read out into an auxiliary memory structure. After the full physical address becomes available, the block is multiplexed down to one set, and a compare is performed on the ways of the set to determine if the requested data is in the cache and, if so, which way the data is in. A device for achieving the method includes a cache index organized into two arrays, each having a number of sets and a number of ways. One of the arrays may used to store micro-tags for way prediction.

Abstract: A microprocessor which includes means for rounding a 68 bit binary number. The rounding bit is calculated based on the precision, rounding mode, and the Guard, Round, and Sticky bits. One path assumes that the number will not be rounded up and pads zeros to the fraction bits according to the precision. Another path assumes that the number will be rounded up. Ones instead of zeros are padded, again, according to the precision. Then, the padded number is incremented by one. Based on the rounding bit, either the non-rounded up path or the rounded up path will be chosen. Thereby, a correctly rounded number with the trailing bits following the least significant bit of the selected precision being zeros results.

Abstract: A memory system (10) is disclosed including a memory array (14), decoder circuit (16), and sensing circuit (17). The memory array includes a plurality of two-port CMOS memory cells (42) arranged in columns and rows that are selectively addressed by the decoder circuit. The bipolar sensing circuit responds to data stored in an addressed memory cell in the following manner. A column decoder (28) in the decoder circuit provides information to a source select multiplexer (30) and a column read access port (18) to selectively couple information stored in the memory cell to an output stage (20). At the output stage a comparison is made between the stored data and a reference voltage provided by a threshold circuit (38) to produce an output indicating the sensed level. The memory cells are preferably asymmetrically designed for hysteretic operation. The resultant bipolar/CMOS memory system advantageously combines the attributes of high density, high speed, and low power consumption.