Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Abstract: Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

Abstract: Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Abstract: The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules analysis can be used to identify specific areas of a layout that can then be analyzed in detail using models. This approach provides numerous advantages. It allows the models-based analysis tool to concentrate upon portions of the layout that requires greater attention and allocate fewer resources towards the areas less critical to the yield.

Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Abstract: Method and system for chip optimization using model based verification (MBV) tool provide more accurate verification in determining hotspots and their characteristics. The MBV and the layout optimizer are implemented within a feedback loop. This type of verification allows for the MBV tool to provide hints, constraints and hotspot information to the layout optimizer. In addition, the model-based simulation results can be used to automatically fix the circuit designs and allow for specialized optimization flow for standard cell libraries.

Abstract: Methods and systems for integrating both models and rules into a verification flow to address both of these issues. Models are employed to perform simulations to provide more accurate verification results. In addition, the lithography simulation results can be used to fine-tune the rules themselves to provide a more realistic check upon circuit designs.

Abstract: Methods and systems for the integration of models and accurate predictions to score the circuit design, which translates to a more accurate and less complex yield prediction. In the present inventive approach, the computer-implemented methods and systems use at least one processor that is configured for performing at least predicting a physical realization of a layout design based at least in part on one or more model parameters, determining one or more hotspots associated with the layout design, determining a score for each of the one or more hotspots associated with the layout design, and categorizing the one or more hotspots according to at least the score in some embodiments. In some embodiments, the methods or the systems further use at least one processor for the act of determining one or more hotspots by using at least the design intent or the manufacturing information.

Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Abstract: Disclosed is an improved method and system for implementing parallel processing of computing operations by effectively handling dependencies between different sequences of computing operations. In some approaches, some or all operations corresponding to dependencies between different sequences of operations are duplicated among the different sequences. This approach may be used to implement parallel processing of EDA tools.