Patents by Inventor Roland Serrano

Roland Serrano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS FOR PROCESSING A SEMICONDUCTOR WAFER, A SEMICONDUCTOR WAFER AND A SEMICONDUCTOR DEVICE
    Publication number: 20130175671
    Abstract: A semiconductor wafer, comprising multiple active areas suitable for providing semiconductor devices or circuits. Inactive areas separate the active areas from each other. The wafer has a stressed layer with a first surface, and another layer which is in contact with the stressed layer along a second surface of the stressed layer, opposite to the first surface. Multiple trench lines, extend in parallel to the first surface of the stressed layer in an inactive area and have a depth less than the thickness of the semiconductor wafer.
    Type: Application
    Filed: September 30, 2010
    Publication date: July 11, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Philippe Renaud, Roland Serrano