Patents by Inventor Roland Sperlich
Roland Sperlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230336083Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.Type: ApplicationFiled: July 19, 2022Publication date: October 19, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Dushmantha Bandara RAJAPAKSHA, Roland SPERLICH, Anant Shankar KAMATH, Vijayalakshmi DEVARAJAN, Wesley RAY
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Patent number: 11443889Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.Type: GrantFiled: June 17, 2020Date of Patent: September 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dushmantha Bandara Rajapaksha, Roland Sperlich, Anant Shankar Kamath, Vijayalakshmi Devarajan, Wesley Ray
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Patent number: 11380631Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.Type: GrantFiled: November 27, 2019Date of Patent: July 5, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dushmantha Bandara Rajapaksha, Vijayalakshmi Devarajan, Roland Sperlich, Wesley Ray
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Publication number: 20210159192Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Dushmantha Bandara Rajapaksha, Vijayalakshmi Devarajan, Roland Sperlich, Wesley Ray
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Patent number: 10880117Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.Type: GrantFiled: December 10, 2019Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abhijeeth Aarey Premanath, Richard Edwin Hubbard, Maxwell Guy Robertson, Lokesh Kumar Gupta, Mark Edward Wentroble, Roland Sperlich, Dejan Radic
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Publication number: 20200402702Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.Type: ApplicationFiled: June 17, 2020Publication date: December 24, 2020Inventors: Dushmantha Bandara RAJAPAKSHA, Roland SPERLICH, Anant Shankar KAMATH, Vijayalakshmi DEVARAJAN, Wesley RAY
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Publication number: 20200136860Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.Type: ApplicationFiled: December 10, 2019Publication date: April 30, 2020Inventors: Abhijeeth AAREY PREMANATH, Richard Edwin HUBBARD, Maxwell Guy ROBERTSON, Lokesh Kumar GUPTA, Mark Edward WENTROBLE, Roland SPERLICH, Dejan RADIC
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Patent number: 10560282Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.Type: GrantFiled: December 26, 2017Date of Patent: February 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abhijeeth Aarey Premanath, Richard Edwin Hubbard, Maxwell Guy Robertson, Lokesh Kumar Gupta, Mark Edward Wentroble, Roland Sperlich, Dejan Radic
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Patent number: 10298238Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: GrantFiled: May 19, 2017Date of Patent: May 21, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich
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Publication number: 20180351765Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.Type: ApplicationFiled: December 26, 2017Publication date: December 6, 2018Inventors: Abhijeeth Aarey Premanath, Richard Edwin Hubbard, Maxwell Guy Robertson, Lokesh Kumar Gupta, Mark Edward Wentroble, Roland Sperlich, Dejan Radic
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Publication number: 20170257098Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: ApplicationFiled: May 19, 2017Publication date: September 7, 2017Inventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich
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Patent number: 9660652Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: GrantFiled: September 8, 2015Date of Patent: May 23, 2017Assignee: Texas Instruments IncorporatedInventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich
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Patent number: 9602318Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.Type: GrantFiled: August 5, 2015Date of Patent: March 21, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Roland Sperlich, Huanzhang Huang, Charles M. Branch
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Publication number: 20160087633Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.Type: ApplicationFiled: September 8, 2015Publication date: March 24, 2016Inventors: Weicheng ZHANG, Huanzhang HUANG, Yanli FAN, Roland SPERLICH
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Publication number: 20150341194Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Inventors: Roland Sperlich, Huanzhang Huang, Charles M. Branch
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Patent number: 9130792Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.Type: GrantFiled: June 9, 2014Date of Patent: September 8, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Roland Sperlich, Huanzhang Huang, Charles M. Branch
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Publication number: 20140362900Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.Type: ApplicationFiled: June 9, 2014Publication date: December 11, 2014Inventors: Roland Sperlich, Huanzhang Huang, Charles M. Branch
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Patent number: 8311083Abstract: Conventional transceivers do provide some compensation for in-phase/quadrature (I/Q) imbalance. However, these techniques do not separately compensate for I/Q imbalance for the transmitter and receiver sides of the transceiver. Here, a transceiver is provided that allows for compensation of I/Q imbalance in the transmitter and receiver irrespective of the other to allow for a more accurate transceiver.Type: GrantFiled: December 29, 2009Date of Patent: November 13, 2012Assignee: Texas Instruments IncorporatedInventors: Lei Ding, Zigang Yang, Fernando Mujica, Roland Sperlich
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Patent number: 8306149Abstract: An apparatus is provided. In the apparatus, an input to index (I2I) module maps a complex input into a real signal. A real data tap delay line is coupled to the I2I module and includes N delay-elements. A complex data tap delay line is configured to receive the complex input and includes M delay elements. A set of K of non-linear function modules is also provided. Each non-linear function module from the set has at least one real input, at least one complex input, and at least one complex output. A configurable connectivity crossbar multiplexer couples K of the N real tap delay line elements to real inputs of the set non-linear functions and couples K of the M complex tap delay line elements to complex inputs of the set non-linear function modules.Type: GrantFiled: October 1, 2009Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Fernando Alberto Mujica, Hardik Prakash Gandhi, Lei Ding, Milind Borkar, Zigang Yang, Roland Sperlich, Lars Morten Jorgensen, William L. Abbott
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Patent number: 8306150Abstract: Systems and methods for identifying a transmission channel response and a feedback channel response from a plurality of composite system responses are disclosed. A plurality of shifted feedback signals are created by shifting a feedback signal frequency by a plurality of first offset values and/or by shifting a transmission signal frequency by a plurality of second offset values. The feedback signals are compared to an input signal to identify the transmission channel response and/or a feedback channel response. A control signal is generated for a pre-distortion circuit to modify the input signal by an inverse of the transmission channel response. The composite system response is measured at a plurality of operating frequencies and at the plurality of offset values. The measurements are stored in a matrix and singular value decomposition is applied to the matrix of measurements to calculate the transmission channel response and feedback channel response.Type: GrantFiled: June 25, 2010Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Fernando A. Mujica, Carson A. Wick, Lei Ding, Milind Borkar, Roland Sperlich