Abstract: A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock driver circuit may be disposed on a second integrated circuit substrate. The programmable clock driver circuit includes a control circuit and a clock generator therein. The control circuit is configured to detect an error(s) in configuration data that is used by the programmable clock driver circuit. This configuration data is read from the nonvolatile memory and stored in volatile program registers during program restore operations. The control circuit is further configured to automatically idle the clock generator in response to detecting the error in the configuration data. This automatic idling of the clock generator may include operations to set the clock generator at a default setting (e.g.

Abstract: An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes. The multi-Q mode of operation supports write path queue switching that is free of write word fall-through and read path queue switching that is free of read word fall-through. The multi-Q mode also supports write path queue switching on every write cycle in both SDR and DDR write modes and independent read path queue switching on every read cycle in both SDR and DDR read modes.

Abstract: An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

Abstract: Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.

Abstract: The present invention provides a circuit for writing a particular sized data word from a common input to a number of individual memory cells in a memory array and reading a particular sized data word from the individual memory cells to a common output. The size of the word written to the memory cells can be larger, smaller or the same as the size of the word read from the memory array. The present invention uses a multi-bit write counter to distribute a write timing signal to a number of multiplexer blocks and a multi-bit read counter to distribute a read timing signal to a number of sense amplifier blocks. Each of the multiplexer blocks receives both a data input signal from the common input and the write timing signal continuously when the circuit is in operation. Each of the sense amplifier blocks receives data from the memory array and a read timing signal at all times.

Abstract: Methods of testing integrated circuits to include data traversal path identification information include the steps of transferring test data into an integrated circuit containing devices therein and then controlling operation of the integrated circuit so that the test data traverses a first path through the devices. At least a portion of the test data and an identification of at least a first portion of the first path are then retrieved from the integrated circuit. This retrieving step may be preceded by the step of overwriting a first portion of the test data with an identification of a first portion of the first path. In the case of a buffer memory device, an identification (e.g., address) of a current write register (receiving test data) may be “tagged” to a series of test words written into the current write register during test mode operation.

Abstract: The present invention provides a design method and apparatus for improving the testing of devices having status flags that indicate when particular boundary conditions are met. The present invention enables a subset of the overall device architecture that requires much less testing and vector analysis to fully analyze the device characteristics. The smaller subset of the device maximizes the number of in-depth analysis tests that can be run to provide a reliable tested device. After the tests are run on the smaller subset of the device, a smaller subset of tests may be executed on the entire full depth array with confidence that the in-depth tests have been previously executed. The present invention method and apparatus can be enabled during design, device characterization and production test phases of the product.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors that are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: Multi-port memory arrays having partitioned registers therein are provided. The registers are partitioned into subarrays so that at least two columns of a selected register can be simultaneously written to (or read from) using first and second input/output driver circuits. These first and second input/output driver circuits are electrically coupled to respective read and write data ports at opposing ends of the memory array. Control logic and first and second input/output driver circuits are provided for writing a first portion of a word of data into a first subarray while simultaneously writing a second portion of the word of data into a second subarray. Here, the first and second portions may comprise the least significant and most significant bytes of the word of data.

Abstract: The present invention concerns a circuit and method to automatically test and disable defective rows in a FIFO or other buffer where the wordlines or rows of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be automatically disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using a comparison circuit to determine if the words read from the memory are accurate. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.

Abstract: The present invention concerns a circuit and method for improving the data access times across boundary reads between cascaded buffers, such as FIFOs, that are connected to a common data output bus. The circuit allows read accesses within a cascaded buffer system to have similar access speeds, i.e., a boundary read is not noticeably slower or faster than any other non-boundary read access from an individual buffer in the system. The circuit may not adversely affect the data sheet or operating system parameters, and imposes minimal chip real estate constraints.

Abstract: The present invention provides a circuit and method for generating a parity bit and checking the parity of data words positioned in the read data path of a memory device or buffer. The parity check mode can detect errors. The parity generation mode generates EVEN or ODD parity as an additional bit. Other devices in the system may generally be configured to accept either EVEN or ODD parity. The parity generation and checking circuit can detect errors in both the data input to the buffer as well as errors created in the storage of the data by the buffer.

Abstract: The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.

Abstract: The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

Abstract: The present invention disables defective rows in a FIFO or other buffer where the word lines of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using one or more laser fuses. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors which are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: The present invention provides a clocking circuit for receiving a particular sized data word from a common input at a fixed frequency, writing the word to a number of individual memory cells in a storage device, reading another particular sized data word from the individual memory cells at a second particular frequency and presenting the data words to a common output at the second frequency. The storage device can be implemented as a memory array but is not limited to a memory array. The size of the words written to the storage device can be larger, smaller or the same as the size of the word read from the storage device. The present invention uses a multi-bit write counter to distribute a write timing signal at a particular frequency to a number of decoder and multiplexer blocks and a multi-bit read counter to distribute a read timing signal at a second particular frequency to a number of sense amplifier blocks.

Abstract: The present invention provides a circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data input signal and the timing signal at all times. When a particular timing signal is present at a given decoder, the input signal containing a fixed width data word is passed through to the corresponding memory array for storing the data word. The present invention reduces the number of internal signal lines necessary to implement the control function and significantly reduces the chip area needed to generate the signal lines.

Abstract: The present invention provides a circuit for distributing data from a number of individual memory cells in a memory array to a common output. The present invention uses a multi-bit counter to distribute a timing signal to a number of sense amplifier blocks. Each of the sense amplifier blocks receives both a data input signal from the memory array and the timing signal at all times. When a particular timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from the corresponding memory array and is presented to the output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to read multiple width words from the memory array.

Abstract: The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any type of advanced testing to be performed on the memory array without regard to the restrictions imposed by the various status flags that may be present. The testing mode can be entered by a completely user-defined mechanism. During this testing mode, the user has complete control over the contents of the memory array and can also have complete control over the positioning of the write word line with respect to the read word line without, for example, any write-read word line pointer equality signals being generated. In one example of the present invention used in a FIFO, testing times required for data retention testing are reduced from approximately six seconds to approximately 500.mu.