Patents by Inventor Roland Vandamme
Roland Vandamme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9566687Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.Type: GrantFiled: October 13, 2014Date of Patent: February 14, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20160101502Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.Type: ApplicationFiled: October 13, 2014Publication date: April 14, 2016Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20140357161Abstract: A polishing head assembly for single side polishing of silicon wafers includes a polishing head and a cap. The polishing head includes a top surface and a bottom surface and defines a longitudinal axis extending therethrough. The cap is positioned coaxially with the polishing head and includes an upper surface and a lower surface. The upper surface is spaced from the bottom surface of the polishing head to form a chamber that allows the cap to deflect toward the polishing head.Type: ApplicationFiled: May 31, 2014Publication date: December 4, 2014Inventors: Sumeet Bhagavat, Peter Albrecht, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20120025353Abstract: A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Guoqiang David Zhang, Roland Vandamme
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Publication number: 20120028555Abstract: A grinding tool for trapezoid grinding of a wafer on a profiling machine includes an annular wheel including a central hole adapted for mounting the wheel on a spindle. The wheel includes at least two grooves disposed at an outer edge of the wheel and the grooves are sized for receiving an outer edge of the wafer. At least one of the grooves is adapted for rough grinding of the wafer. At least one other of the grooves is adapted for fine grinding of the wafer.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Guoqiang David Zhang, Roland Vandamme, Peter D. Albrecht
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Patent number: 8066553Abstract: A hydrostatic pad for use in holding a semiconductor wafer during grinding of the wafer by grinding wheels. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.Type: GrantFiled: January 20, 2005Date of Patent: November 29, 2011Assignee: MEMC Electronic Materials, Inc.Inventors: Milind S. Bhagavat, Puneet Gupta, Roland Vandamme, Takuto Kazama, Noriyuki Tachi
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Publication number: 20090242126Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Henry F. Erk, Peter D. Albrecht, Eugene R. Hollander, Thomas E. Doane, Judith A. Schmidt, Roland Vandamme, Guoqiang (David) Zhang
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Patent number: 7559825Abstract: Semiconductor wafers have a front surface, a back surface, a notch, and an edge. A method of polishing a wafer includes polishing at least one of the surfaces and the notch of the wafer using a polishing pad and slurry. At least one surface of the wafer is cleaned of residual slurry. The cleaned surface is grasped by applying a vacuum to the cleaned surface of the wafer using a vacuum chuck. Edge of the wafer is polished using a pad and slurry while the wafer is grasped by the vacuum chuck.Type: GrantFiled: December 21, 2006Date of Patent: July 14, 2009Assignee: MEMC Electronic Materials, Inc.Inventors: Henry Frank Erk, Judith Ann Schmit, Roland Vandamme
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Patent number: 7416962Abstract: A method is provided for processing the back side of a semiconductor wafer after the wafer has been lapped. The process includes grinding the back side of the wafer to remove wafer material, to substantially eliminate lap damage from the back side of the wafer. The back side of the wafer may then be cleaned, etched, and polished, after which the front side of the wafer is polished. The back side grinding may be accomplished after the lapping without any other step of substantial removal of wafer material. The polishing of the back side of the wafer may be performed with a CMP machine and may produce a specular surface, visually free of damage under haze lamp inspection, with removal of about 0.5 microns of wafer material. After polishing the front side of the wafer, an epitaxial layer may be produced on the front side of the wafer.Type: GrantFiled: August 30, 2002Date of Patent: August 26, 2008Assignee: Siltronic CorporationInventors: Wesley Harrison, Roland Vandamme, David Gore
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Publication number: 20080153391Abstract: Semiconductor wafers have a front surface, a back surface, a notch, and an edge. A method of polishing a wafer includes polishing at least one of the surfaces and the notch of the wafer using a polishing pad and slurry. At least one surface of the wafer is cleaned of residual slurry. The cleaned surface is grasped by applying a vacuum to the cleaned surface of the wafer using a vacuum chuck. Edge of the wafer is polished using a pad and slurry while the wafer is grasped by the vacuum chuck.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Henry Frank Erk, Judith Ann Schmit, Roland Vandamme
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Publication number: 20080020684Abstract: A hydrostatic pad for use in holding a semiconductor wafer during grinding of the wafer by grinding wheels. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.Type: ApplicationFiled: January 20, 2005Publication date: January 24, 2008Applicant: MEMC ELECTRONIC MATERIALS, INCORPORATEDInventors: Milind Bhagavat, Puneet Gupta, Roland Vandamme, Takuto Kazama, Noriyuki Tachi
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Publication number: 20070179660Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.Type: ApplicationFiled: December 28, 2006Publication date: August 2, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Sumeet Bhagavat, Milind Bhagavat, Roland Vandamme, Tomomi Komura
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Publication number: 20070178807Abstract: A system and method for slicing an ingot into wafers using the wire saw process. A slurry collection system collects and supplies slurry to a slurry handling system for controlling temperatures and/or flow rates of the slurry thereby providing slurry output at a controlled temperature and/or a controlled flow rate to slicing system for cutting the ingot, which may be preheated.Type: ApplicationFiled: January 10, 2007Publication date: August 2, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Puneet Gupta, Milind Kulkarni, Carlo Zavattari, Roland Vandamme
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Publication number: 20070179659Abstract: A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.Type: ApplicationFiled: December 28, 2006Publication date: August 2, 2007Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Roland Vandamme, Milind Bhagavat
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Publication number: 20040043616Abstract: A method is provided for processing the back side of a semiconductor wafer after the wafer has been lapped. The process includes grinding the back side of the wafer to remove wafer material, to substantially eliminate lap damage from the back side of the wafer. The back side of the wafer may then be cleaned, etched, and polished. after which the front side of the wafer is polished. The back side grinding may be accomplished after the lapping without any other step of substantial removal of wafer material. The polishing of the back side of the wafer may be performed with a CMP machine and may produce a specular surface, visually free of damage under haze lamp inspection, with removal of about 0.5 microns of wafer material. After polishing the front side of the wafer, an epitaxial layer may be produced on the front side of the wafer.Type: ApplicationFiled: August 30, 2002Publication date: March 4, 2004Inventors: Wesley Harrison, Roland Vandamme, David Gore
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Patent number: 6200908Abstract: A process for reducing the waviness of a semiconductor wafer utilizing plasma assisted chemical etching is disclosed. The process includes measuring the surface profile at discrete points on one surface of the wafer independent from the apposing surface, computing a dwell time versus position map based on the measured surface profiles, and selectively removing material from each surface of the wafer by plasma assisted chemical etching to reduce the waviness of the wafer.Type: GrantFiled: August 4, 1999Date of Patent: March 13, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Roland Vandamme, Ankur Desai, Dale Witte, Yun-Biao Xin
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Patent number: 6114245Abstract: A method of processing a semiconductor wafer comprises rough grinding the front and back surfaces of the wafer to quickly reduce the thickness of the wafer. The front and back surfaces are then lapped with a lapping slurry to further reduce the thickness of the wafer and reduce damage caused by the rough grinding. Lapping time is reduced by provision of the rough grinding step. The wafer is etched in a chemical etchant to further reduce the thickness of the wafer and the front surface of the wafer is polished using a polishing slurry to reduce the thickness of the wafer down to a predetermined final wafer thickness. A fine grinding step may be added to eliminate lapping and/or reduce polishing time.Type: GrantFiled: July 19, 1999Date of Patent: September 5, 2000Assignee: MEMC Electronic Materials, Inc.Inventors: Roland Vandamme, Yun-Biao Xin, Zhijian Pei