Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.

Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.

Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.

Abstract: Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.

Abstract: A method is provided for forming an opening in a layer of a selected material. The method comprises, forming a polymer resist layer over said selected material and plasticising areas of the resist where openings are to be formed. The plasticising is performed by depositing a first solution onto the surface of said polymer resist layer, where the first solution is a plasticiser selected to increase permeability of the polymer resist layer to a second solution, in an area which has absorbed the first solution. The second solution is selected to be an etchant or solvent for the selected material. After the resist layer has been selectively plasticised, it is contacted with the second solution, which permeates the polymer resist layer in the area of increased permeability and forms an opening in the selected material.

Abstract: A method is provided for forming an opening in a layer of a selected material. The method comprises, forming a polymer resist layer over said selected material and plasticising areas of the resist where openings are to be formed. The plasticising is performed by depositing a first solution onto the surface of said polymer resist layer, where the first solution is a plasticiser selected to increase permeability of the polymer resist layer to a second solution, in an area which has absorbed the first solution. The second solution is selected to be an etchant or solvent for the selected material. After the resist layer has been selectively plasticised, it is contacted with the second solution, which permeates the polymer resist layer in the area of increased permeability and forms an opening in the selected material.