Patents by Inventor Rolando H. Bruce

Rolando H. Bruce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200151098
    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.
    Type: Application
    Filed: October 14, 2019
    Publication date: May 14, 2020
    Applicant: BITMICRO LLC
    Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
  • Patent number: 10540242
    Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 21, 2020
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Richard A. Cantong, Marizonne Operio Fuentes
  • Patent number: 10445239
    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 15, 2019
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
  • Publication number: 20190220373
    Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data,
    Type: Application
    Filed: January 15, 2019
    Publication date: July 18, 2019
    Applicant: BITMICRO LLC
    Inventors: Rolando H. Bruce, Richard A. Cantong, Marizonne Operio Fuentes
  • Patent number: 10210084
    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 19, 2019
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
  • Patent number: 10180887
    Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: January 15, 2019
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Richard A. Cantong, Marizonne O. Fuentes
  • Patent number: 10082966
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 25, 2018
    Assignee: BiTMICRO LLC
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Patent number: 9734067
    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 15, 2017
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
  • Patent number: 9484103
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: November 1, 2016
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Patent number: 9430386
    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 30, 2016
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
  • Patent number: 9372755
    Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: June 21, 2016
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Leonila T. Bruce, Richard A. Cantong, Marizonne O. Fuentes
  • Patent number: 9099187
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 4, 2015
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Publication number: 20150012690
    Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.
    Type: Application
    Filed: March 17, 2014
    Publication date: January 8, 2015
    Inventors: ROLANDO H. BRUCE, ELMER PAULE DELA CRUZ, MARK IAN ALCID ARCEDERA
  • Publication number: 20140104949
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Application
    Filed: September 26, 2013
    Publication date: April 17, 2014
    Applicant: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan Lanuza, Jose Lukban, Mark Arcedera, Ryan Chong
  • Patent number: 8560804
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: October 15, 2013
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Publication number: 20110113186
    Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
    Type: Application
    Filed: September 14, 2010
    Publication date: May 12, 2011
    Applicant: BiTMICRO Networks, Inc.
    Inventors: Rolando H. Bruce, Rayjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
  • Patent number: 6970890
    Abstract: A method for recovering data in a storage device is provided in which information related to a first data structure is defined with a plurality of copies of a second data structure and the information related to the first data structure is rebuilt using the plurality of copies of the second data structure upon corruption thereof.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: November 29, 2005
    Assignee: BiTMicro Networks, Inc.
    Inventors: Ricardo H. Bruce, Rolando H. Bruce
  • Patent number: 6529416
    Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: March 4, 2003
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Ricardo H. Bruce, Rolando H. Bruce
  • Publication number: 20020141244
    Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.
    Type: Application
    Filed: May 28, 2002
    Publication date: October 3, 2002
    Inventors: Ricardo H. Bruce, Rolando H. Bruce
  • Publication number: 20020097594
    Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.
    Type: Application
    Filed: March 27, 2001
    Publication date: July 25, 2002
    Inventors: Ricardo H. Bruce, Rolando H. Bruce