Patents by Inventor Rolando H. Bruce
Rolando H. Bruce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200151098Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.Type: ApplicationFiled: October 14, 2019Publication date: May 14, 2020Applicant: BITMICRO LLCInventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
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Patent number: 10540242Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.Type: GrantFiled: January 15, 2019Date of Patent: January 21, 2020Assignee: BiTMICRO LLCInventors: Rolando H. Bruce, Richard A. Cantong, Marizonne Operio Fuentes
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Patent number: 10445239Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.Type: GrantFiled: July 31, 2017Date of Patent: October 15, 2019Assignee: BiTMICRO LLCInventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
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Publication number: 20190220373Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data,Type: ApplicationFiled: January 15, 2019Publication date: July 18, 2019Applicant: BITMICRO LLCInventors: Rolando H. Bruce, Richard A. Cantong, Marizonne Operio Fuentes
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Patent number: 10210084Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.Type: GrantFiled: August 29, 2016Date of Patent: February 19, 2019Assignee: BiTMICRO LLCInventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
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Patent number: 10180887Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.Type: GrantFiled: June 8, 2016Date of Patent: January 15, 2019Assignee: BiTMICRO LLCInventors: Rolando H. Bruce, Richard A. Cantong, Marizonne O. Fuentes
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Patent number: 10082966Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.Type: GrantFiled: September 19, 2016Date of Patent: September 25, 2018Assignee: BiTMICRO LLCInventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
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Patent number: 9734067Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.Type: GrantFiled: April 16, 2015Date of Patent: August 15, 2017Assignee: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
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Patent number: 9484103Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.Type: GrantFiled: July 20, 2015Date of Patent: November 1, 2016Assignee: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
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Patent number: 9430386Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.Type: GrantFiled: March 17, 2014Date of Patent: August 30, 2016Assignee: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Elmer Paule Dela Cruz, Mark Ian Alcid Arcedera
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Patent number: 9372755Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.Type: GrantFiled: October 5, 2011Date of Patent: June 21, 2016Assignee: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Leonila T. Bruce, Richard A. Cantong, Marizonne O. Fuentes
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Patent number: 9099187Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.Type: GrantFiled: September 26, 2013Date of Patent: August 4, 2015Assignee: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
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Publication number: 20150012690Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.Type: ApplicationFiled: March 17, 2014Publication date: January 8, 2015Inventors: ROLANDO H. BRUCE, ELMER PAULE DELA CRUZ, MARK IAN ALCID ARCEDERA
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Publication number: 20140104949Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.Type: ApplicationFiled: September 26, 2013Publication date: April 17, 2014Applicant: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Reyjan Lanuza, Jose Lukban, Mark Arcedera, Ryan Chong
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Patent number: 8560804Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.Type: GrantFiled: September 14, 2010Date of Patent: October 15, 2013Assignee: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Reyjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
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Publication number: 20110113186Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.Type: ApplicationFiled: September 14, 2010Publication date: May 12, 2011Applicant: BiTMICRO Networks, Inc.Inventors: Rolando H. Bruce, Rayjan C. Lanuza, Jose Miguel N. Lukban, Mark Ian A. Arcedera, Ryan C. Chong
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Patent number: 6970890Abstract: A method for recovering data in a storage device is provided in which information related to a first data structure is defined with a plurality of copies of a second data structure and the information related to the first data structure is rebuilt using the plurality of copies of the second data structure upon corruption thereof.Type: GrantFiled: March 27, 2001Date of Patent: November 29, 2005Assignee: BiTMicro Networks, Inc.Inventors: Ricardo H. Bruce, Rolando H. Bruce
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Patent number: 6529416Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.Type: GrantFiled: March 27, 2001Date of Patent: March 4, 2003Assignee: BiTMICRO Networks, Inc.Inventors: Ricardo H. Bruce, Rolando H. Bruce
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Publication number: 20020141244Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.Type: ApplicationFiled: May 28, 2002Publication date: October 3, 2002Inventors: Ricardo H. Bruce, Rolando H. Bruce
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Publication number: 20020097594Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.Type: ApplicationFiled: March 27, 2001Publication date: July 25, 2002Inventors: Ricardo H. Bruce, Rolando H. Bruce