Abstract: A single metal-plate bypass capacitor (10) includes a metal top plate (26) separated from a silicon substrate (12) by a thermally-grown, silicon dioxide dielectric (16) layer. An additional silicon plate (36) can be included intermediate to the metal top plate (26) and the silicon substrate (12) for multiple power supply devices. The silicon substrate (12) is electrically accessed through a metal contact pad (28) overlying a doped region (34) of the silicon substrate (12). The metal contact pad (28) is electrically isolated from the top plate (26) by an isolation structure (30). The bypass capacitor (10) is designed to be attached directly to the top surface of a semiconductor device (18), which enables the bypass capacitor (10) to be interconnected to the semiconductor device (18) by a plurality of bonding wires (25) having a minimal length. Because the capacitor dielectric (16) is formed as a very thin layer by the thermal oxidation of silicon, the self-inductance of bypass capacitor (10) is minimized.

Abstract: Electrical parasitic parameters can lead to reflections and switching noise in a circuit causing signal distortions. A stripline configuration semiconductor device (10) can be manufactured to reduce the overall parasitic parameters, especially inductance, of a device. In one embodiment, a semiconductor die (12) having a grounded backside (20) is directly bonded with an electrically conductive adhesive (22) to a metal base (16), thus grounding the metal base. The die is also electrically connected to a leadframe (14) by wire bonds (24). An electrically insulating adhesive (28) is used to seal a metal lid (18) to the metal base with the die and leadframe disposed between the lid and base, thus forming a protective package body. The lid is grounded to a ground lead (26) of the leadframe with a solder bridge (30). An additional advantage to having a metal package body is that it provides shielding for the device.

Abstract: A semiconductor device (10) has a multilayer leadframe (14) with two full voltage planes, specifically an upper voltage plane (16) and a lower voltage plane (18). A semiconductor die (12) is mounted to the upper voltage plane. Bond pads (13) of the die are electrically coupled to appropriate leads (20a, 20b, and 20c) using conductive wires (22). Upper voltage plane (16) is provided with at least one opening (28) to allow passage of a conductive wire through the opening in order to electrically couple a bond pad or a lead to lower voltage plane (18). The voltage planes are attached to the leadframe using welded conductive tabs (24), an electrically insulating adhesive layer (26), or both.