Abstract: An event manager for filtering safety and security events of a system including an event sequence list including predetermined event sequences in which each sequence includes at least one event identifier identifying a corresponding one of multiple monitored events, an event sequence array that stores a received event sequence in response to received event notifications, and a controller that stores an event identifier into the event sequence array and that determines whether the received event sequence matches at least one of the predetermined event sequences for determining a composite event and a response for each received event notification. The matching determination may be made with or without consideration of chronological order. A suspected composite event may be identified when multiple possible matches may exist, and a final composite event is ratified when only one match is found. An exception may be generated upon timeout of a timer.

Abstract: An architecture for monitoring, analyzing, and reacting to safety and cybersecurity events has been disclosed. In at least one embodiment, a method for processing safety and security events of a system includes requesting a reaction or escalating an effect from a first controller of the system to a second controller of the system based on a subset of available reactions for a current context of the system, constraint information, a predetermined effect-reaction policy, and the effect.

Abstract: The present application relates to an apparatus for verifying fragment processing related data and a method of operating thereof. The fragment shader unit is coupled to the at least one data buffer. A fragment shader unit of a graphics processing pipeline receives fragment data and records fragment processing related data in the at least one data buffer on processing one or more fragments in accordance with the received fragment data. A comparator unit coupled to the at least one data buffer compares the recorded fragment processing related data in the at least one data buffer to reference data and issues a fault indication signal in case the recorded fragment processing related data and the reference data mismatch.

Abstract: The present application relates to an apparatus for verifying the integrity of image data comprising mapped texture data is provided and a method of operating thereof. A fragment shader unit is coupled to first and second frame buffers and at least one texture buffer. A first texture sampler unit is configured to output texture mapped fragments to the first frame buffer. A second texture sampler unit is configured to output texture mapped fragments to the second frame buffer. A comparator unit is further configured to compare the image data stored in the first frame buffer and in the second frame buffer. A fault indication signal is issued in case the image data of the first and the second frame buffers mismatch.

Abstract: High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.

Abstract: The present application relates to an apparatus for verifying fragment processing related data and a method of operating thereof. The fragment shader unit is coupled to the at least one data buffer. A fragment shader unit of a graphics processing pipeline receives fragment data and records fragment processing related data in the at least one data buffer on processing one or more fragments in accordance with the received fragment data. A comparator unit coupled to the at least one data buffer compares the recorded fragment processing related data in the at least one data buffer to reference data and issues a fault indication signal in case the recorded fragment processing related data and the reference data mismatch.

Abstract: The present application relates to an apparatus for verifying the integrity of transformed vertex data and a method of operating thereof. The apparatus comprises a graphics processing pipeline with a vertex shader unit, a buffer and a comparator unit. The vertex shader unit receives a stream of vertex data according to a vertex specification. The vertex shader unit applies a transformation on each of the vertices in the received stream of vertex data to and outputs a stream of transformed vertex data. The buffer is coupled to the vertex shader unit to buffer the transformed vertex data. The comparator is further configured to verify the integrity of at least a subset of the transformed vertex data on the basis of reference data and to issue a fault indication signal in case the verification fails.

Abstract: The present application relates to an apparatus for verifying the integrity of image data comprising mapped texture data is provided and a method of operating thereof. A fragment shader unit is coupled to first and second frame buffers and at least one texture buffer. A first texture sampler unit is configured to output texture mapped fragments to the first frame buffer. A second texture sampler unit is configured to output texture mapped fragments to the second frame buffer. A comparator unit is further configured to compare the image data stored in the first frame buffer and in the second frame buffer. A fault indication signal is issued in case the image data of the first and the second frame buffers mismatch.

Abstract: The present application relates to an apparatus for verifying the origin of texture data and a method of operating thereof. The apparatus comprises a frame buffer; at least one texture buffer; a graphics processing pipeline with a fragment shader unit; and a comparator unit. The at least one texture buffer is provided to store texture data and test texture data. The fragment shader unit maps the test texture data retrieved from the texture buffer on a predefined area of the image data stored in the frame buffer. The comparator unit extracts image data values located in the predefined area of the image data stored in the frame buffer; compares the extracted image data with reference data and issues a fault indication signal in case the extracted image data and the reference data mismatch.

Abstract: High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.