Abstract: Circuit comprising a signal input (11) for receiving an input signal (s(t)) and a digital output stage (15) being designed for operation at a supply voltage (VDD). The output stage (15) comprises a series of two n-channel CMOS transistors (no1, no2), a common node (17) between the two n-channel CMOS transistors (no1, no2), and an output port (16). Active voltage limiting means (14) are arranged between the signal input (11) and the common node (17) for limiting voltages (VNM) at the common node (17) to a voltage limit (Vmax). The voltage limiting means (14) are controllable byte state of the input signal (s(t)).

Abstract: A telephone set includes an anti-sidetone circuit formed by a feedback loop having a filter in the feedback path. The feedback loop output is substantially equal to the signal produced at the set connection terminals by the microphone. Preferably the filter is composed of two sub-filters connected in cascade, formed of switched capacitors in an integrated circuit. An EEPROM control circuit can be included to permit easy programming during manufacture, to match a selected transmission line impedance.