Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: An improved method to compensate for coupling overhead in a distributed computing system offering a raw processing capacity, comprising an effective processing capacity (404) and the coupling overhead, is disclosed, wherein the distributed computing system comprises at least one computer system and at least one coupling facility. The method comprises determining a coupling efficiency, determining and adding an amount of missing processing capacity to the effective processing capacity based on the coupling efficiency in a way that the effective processing capacity of the raw processing capacity corresponds to a billable target processing capacity.

Abstract: An improved method to compensate for coupling overhead in a distributed computing system offering a raw processing capacity, comprising an effective processing capacity (404) and the coupling overhead, is disclosed, wherein the distributed computing system comprises at least one computer system and at least one coupling facility. The method comprises determining a coupling efficiency, determining and adding an amount of missing processing capacity to the effective processing capacity based on the coupling efficiency in a way that the effective processing capacity of the raw processing capacity corresponds to a billable target processing capacity.

Abstract: An improved method to compensate for coupling overhead in a distributed computing system offering a raw processing capacity, comprising an effective processing capacity (404) and the coupling overhead, is disclosed, wherein the distributed computing system comprises at least one computer system and at least one coupling facility. The method comprises determining a coupling efficiency, determining and adding an amount of missing processing capacity to the effective processing capacity based on the coupling efficiency in a way that the effective processing capacity of the raw processing capacity corresponds to a billable target processing capacity.

Abstract: Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

Abstract: A method and logic circuit for a resource management finite state machine (RM FSM) managing resource(s) required by a protocol FSM. After receiving a resource request vector, the RM FSM determines not all of the required resource(s) are available. The protocol FSM transitions to a new state, generates an output vector, and loads the output vector into an output register. The RM FSM transitions to a state indicating that not all the resources are available and freezes an input register. In a subsequent cycle, the RM FSM freezes the output register and a current state register, and forces the output vector to be seen by the FSM environment as a null token. After determining that the required resource(s) are available, the RM FSM transitions to another state indicating that the resources are available, enables the output vector to be seen by the FSM environment, and unfreezes the protocol FSM.

Abstract: An improved method to compensate for coupling overhead in a distributed computing system offering a raw processing capacity, comprising an effective processing capacity (404) and the coupling overhead, is disclosed, wherein the distributed computing system comprises at least one computer system and at least one coupling facility. The method comprises determining a coupling efficiency, determining and adding an amount of missing processing capacity to the effective processing capacity based on the coupling efficiency in a way that the effective processing capacity of the raw processing capacity corresponds to a billable target processing capacity.

Abstract: A method and logic circuit for a resource management finite state machine (RM FSM) managing resource(s) required by a protocol FSM. After receiving a resource request vector, the RM FSM determines not all of the required resource(s) are available. The protocol FSM transitions to a new state, generates an output vector, and loads the output vector into an output register. The RM FSM transitions to a state indicating that not all the resources are available and freezes an input register. In a subsequent cycle, the RM FSM freezes the output register and a current state register, and forces the output vector to be seen by the FSM environment as a null token. After determining that the required resource(s) are available, the RM FSM transitions to another state indicating that the resources are available, enables the output vector to be seen by the FSM environment, and unfreezes the protocol FSM.

Abstract: The invention relates to a method of optimizing a state transition function specification for a state machine engine based on a probability distribution for the state transitions. For the preferred embodiment of the invention, a B-FSM state machine engine accesses a transition rule memory using a processor cache. The invention allows improving the cache hit rate by exploiting the probability distribution. The N transition rules that comprise a hash table entry will be loaded in a burst mode from the main memory, from which the N transition rules are transferred to the processor cache. Because the comparison of the actual state and input values against each of the transition rules can immediately start after each of these rules has been received, the overall performance is improved as the transition rule that is most likely to be selected is the first to be transferred as part of the burst access.

Abstract: The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.

Abstract: A system and method of implementing multiple programmable finite state machines using a shared transition table is disclosed, the method including forming a plurality of finite state machine cores such that an amount of the plurality of finite state machine cores is unchangeable, forming a state transition array, and forming a routing network such that the forming the plurality of associated state transition elements is realized.

Abstract: Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

Abstract: The present, invention improves the hash table lookup operation by using a new processor cache architecture. A speculative processing of entries stored in the cache is combined with a delayed evaluation of cache entries. The speculative processing means that for each cache entry retrieved from main memory in a step of the hash table lookup operation it is assumed that it already contains the selected hash table entry. The delayed evaluation means that certain steps of the lookup operation are performed in parallel with others. In advantageous embodiments the invention can also be used in conjunction with a hierarchy of inclusive caches. The preferred embodiments of the invention involve a new approach for a transition rule cache of a BaRT-FSM controller.

Abstract: The invention relates to a method of optimizing a state transition function specification for a state machine engine based on a probability distribution for the state transitions. For the preferred embodiment of the invention, a B-FSM state machine engine accesses a transition rule memory using a processor cache. The invention allows improving the cache hit rate by exploiting the probability distribution. The N transition rules that comprise a hash table entry will be loaded in a burst mode from the main memory, from which the N transition rules are transferred to the processor cache. Because the comparison of the actual state and input values against each of the transition rules can immediately start after each of these rules has been received, the overall performance is improved as the transition rule that is most likely to be selected is the first to be transferred as part of the burst access.