Abstract: In various embodiments, a memory cell arrangement is provided including a memory cell driver and one or more memory cells, wherein one or more control nodes of each of the one or more memory cells are electrically conductively connected to one or more output nodes of the memory cell driver. The memory cell driver may include: a first supply node to receive a first supply voltage and a second supply node to receive a second supply voltage, a plurality of input nodes to receive a plurality of input voltages, one or more output nodes, and a logic circuit connected to the first supply node, the second supply node, the plurality of input nodes, and the one or more output nodes, wherein the logic circuit includes one or more logic gates and is configured to connect via the one or more logic gates either the first supply node or the second supply node to the one or more output nodes in response to the plurality of input voltages.

Abstract: A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.

Abstract: In various embodiments, a memory cell arrangement is provided including a memory cell driver and one or more memory cells, wherein one or more control nodes of each of the one or more memory cells are electrically conductively connected to one or more output nodes of the memory cell driver. The memory cell driver may include: a first supply node to receive a first supply voltage and a second supply node to receive a second supply voltage, a plurality of input nodes to receive a plurality of input voltages, one or more output nodes, and a logic circuit connected to the first supply node, the second supply node, the plurality of input nodes, and the one or more output nodes, wherein the logic circuit includes one or more logic gates and is configured to connect via the one or more logic gates either the first supply node or the second supply node to the one or more output nodes in response to the plurality of input voltages.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.

Abstract: In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.

Abstract: A receiver and method for operating a receiver, in particular of a radio network, is provided, whereby the receiver includes circuit blocks in a receive path for detecting a preamble of a received signal, and a controller for controlling a receive mode. Whereby at least some of the circuit blocks are designed to be capable of being turned on for a turn-on duration and turned off for a turn-off duration. Whereby, the controller is configured to alternately turn on at least some of the circuit blocks for the turn-on duration and off for the turn-off duration during the receive mode, wherein the turn-off duration is shorter than the preamble.

Abstract: In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.

Abstract: In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.

Abstract: A receiver and method for operating a receiver, in particular of a radio network, is provided, whereby the receiver includes circuit blocks in a receive path for detecting a preamble of a received signal, and a controller for controlling a receive mode. Whereby at least some of the circuit blocks are designed to be capable of being turned on for a turn-on duration and turned off for a turn-off duration. Whereby, the controller is configured to alternately turn on at least some of the circuit blocks for the turn-on duration and off for the turn-off duration during the receive mode, wherein the turn-off duration is shorter than the preamble.

Abstract: A digital radio network, a circuit of a node of a digital radio network, and method for setting up a digital radio network is provided, wherein a transmission power of the first node is set for a radio link between a first node of the digital radio network and a second node of the digital radio network. A sensitivity of a receiving circuit of the second node is set by programming a threshold with which a field-strength-dependent signal is compared. Signal processing of a received and digitized received signal by the second node is activated when the field-strength-dependent signal reaches or exceeds the programmed threshold.

Abstract: A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N?2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of t

Abstract: A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Abstract: A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N?2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of t

Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Abstract: A tunable constant GM circuit allows to compensate for temperature and process variations with high precision by correspondingly adjusting a resistance value and/or the ratio of transistor widths. Thus, in switched capacitor circuits the frequency behaviour, such as the settling time, may be controlled by providing a compensated bias to the transconductance amplifiers typically used in these circuits.