Patents by Inventor Rolf Kassa
Rolf Kassa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210374069Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: ApplicationFiled: August 17, 2021Publication date: December 2, 2021Applicant: Intel CorporationInventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Publication number: 20200242046Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: ApplicationFiled: September 4, 2019Publication date: July 30, 2020Inventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Patent number: 10474471Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.Type: GrantFiled: April 18, 2016Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Justin E. Gottschlich, Klaus Danne, Cristiano L. Pereira, Gilles A. Pokam, Rolf Kassa, Shiliang Hu, Tim Kranich
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Patent number: 10445244Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: GrantFiled: December 19, 2016Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Patent number: 10445245Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: GrantFiled: December 19, 2016Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Patent number: 10394561Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.Type: GrantFiled: October 19, 2016Date of Patent: August 27, 2019Assignee: INTEL CORPORATIONInventors: Nathan D. Dautenhahn, Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Shiliang Hu, Klaus Danne, Rolf Kassa
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Patent number: 10083033Abstract: A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.Type: GrantFiled: March 10, 2015Date of Patent: September 25, 2018Assignee: Intel CorporationInventors: Sebastian Winkel, Girish Venkatasubramanian, Tyler N. Sondag, Rolf Kassa
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Patent number: 9965320Abstract: A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.Type: GrantFiled: December 27, 2013Date of Patent: May 8, 2018Assignee: INTEL CORPORATIONInventors: Rolf Kassa, Justin E. Gottschlich, Shiliang Hu, Gilles A. Pokam, Robert C. Knauerhase
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Patent number: 9934155Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: GrantFiled: December 20, 2012Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Patent number: 9875108Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.Type: GrantFiled: March 16, 2013Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Gilles A. Pokam, Rolf Kassa, Klaus Danne, Tim Kranich, Cristiano L. Pereira, Justin E. Gottschlich, Shiliang Hu
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Publication number: 20170199825Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: ApplicationFiled: December 19, 2016Publication date: July 13, 2017Inventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Publication number: 20170192904Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: ApplicationFiled: December 19, 2016Publication date: July 6, 2017Inventors: Edward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Patent number: 9697040Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.Type: GrantFiled: March 26, 2014Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Justin E. Gottschlich, Gilles A. Pokam, Shiliang Hu, Rolf Kassa, Youfeng Wu, Irina Calciu
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Publication number: 20170039070Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.Type: ApplicationFiled: October 19, 2016Publication date: February 9, 2017Inventors: NATHAN D. DAUTENHAHN, JUSTIN GOTTSCHLICH, GILLES POKAM, CRISTIANO PEREIRA, SHILIANG HU, KLAUS DANNE, ROLF KASSA
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Patent number: 9501340Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.Type: GrantFiled: March 15, 2013Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Nathan D. Dautenhahn, Justin E. Gottschlich, Gilles Pokam, Cristiano L. Pereira, Shiliang Hu, Klaus Danne, Rolf Kassa
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Publication number: 20160299760Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.Type: ApplicationFiled: April 18, 2016Publication date: October 13, 2016Applicant: Intel CorporationInventors: Justin E. Gottschlich, Klaus Danne, Cristiano L. Pereira, Gilles A. Pokam, Rolf Kassa, Shiliang Hu, Tim Kranich
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Publication number: 20160266901Abstract: A method and apparatus are described for efficient register reclamation. For example, one embodiment of an apparatus comprises: single usage detection and tagging logic to examine a sequence of instructions to detect logical registers used by the sequence of instructions that have a single use and to tag an instruction as a single usage instruction if the instruction is a consumer of a logical register that has a single use; an allocator to allocate processor resources to execute the sequence of instructions, the processor resources including physical registers mapped to logical registers to execute the sequence of instructions; and register reclamation logic to free up a logical to physical mapping of a single use register in response to detecting the tag provided by the instruction tagging logic.Type: ApplicationFiled: March 10, 2015Publication date: September 15, 2016Inventors: SEBASTIAN WINKEL, GIRISH VENKATASUBRAMANIAN, TYLER N. SONDAG, ROLF KASSA
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Patent number: 9317297Abstract: Embodiments may provide a method for performing a replay of a previous execution of a program. The method includes generating an order of recorded chunks of instructions across a plurality of recorded threads based, at least in part, on log files generated from the previous execution of the program. The method includes initiating execution of the program, the executing program having a plurality of threads, each thread having a number of chunks of instructions. The method includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk before the instruction is executed. The method includes determining, by a replay module executing on the processor, that the chunk is an active chunk if the chunk is currently in line for execution according to the order of recorded chunks, and responsive to a determination that the chunk is the active chunk, executing the instruction.Type: GrantFiled: September 27, 2012Date of Patent: April 19, 2016Assignee: Intel CorporationInventors: Justin E. Gottschlich, Klaus Danne, Cristiano L. Pereira, Gilles A. Pokam, Rolf Kassa, Shiliang Hu, Tim Kranich
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Patent number: 9244855Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.Type: GrantFiled: December 31, 2007Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Ed Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
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Publication number: 20150277968Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Inventors: Justin E. Gottschlich, Gilles A. Pokam, Shiliang Hu, Rolf Kassa, Youfeng Wu, Irina Calciu