Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A signal acquisition device which receives an input signal, a physical data and a timing data to generate an output data. The signal acquisition device keeps monitoring the input signal for a valid edge. When a valid edge is detected, the signal acquisition device reads the physical data from a physical data processing module and a timing data from a timing module to generate the output data which comprises the new state of the input signal, the physical data and the timing data. The output data is written to a storage arrangement and also sent out to CPU or any other devices.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.