Patents by Inventor Rolf Riesen

Rolf Riesen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250139010
    Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global load from a first address of a shared memory, the shared memory being shared by the nodes, the first address being an address within a shared memory section of a second node, the first address being cached in a first cache of the first node, the executing including: fetching a value stored in the shared memory, at the first address.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Alan GARA, Douglas JOSEPH, Arun RODRIGUES, Samantika SURY, Rolf RIESEN, Robert WISNIEWSKI
  • Publication number: 20250139007
    Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory, the shared memory being shared by the nodes, wherein: each of the nodes includes a hardware-maintained coherence domain and is connected to the other nodes, and each of the nodes includes a respective portion of the shared memory.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Alan GARA, Douglas JOSEPH, Arun RODRIGUES, Samantika SURY, Rolf RIESEN, Robert WISNIEWSKI
  • Publication number: 20250139012
    Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: executing, by a first node of a plurality of nodes, a global clean, the executing including: determining that a first cached value in a cache of the first node is a modified cached copy of data in a shared memory, the shared memory being shared by the nodes; and in response to determining that the first cached value is a modified cached copy of data in the shared memory, writing back the first cached value to the shared memory.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Alan GARA, Douglas JOSEPH, Arun RODRIGUES, Samantika SURY, Rolf RIESEN, Robert WISNIEWSKI
  • Patent number: 12248808
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to relocate a compute thread, the apparatus comprising control circuitry to maintain a location of a plurality of domain access counters associated with a plurality of compute-memory domains for a first compute thread, and an execution monitor to set a first domain access counter of the plurality of domain access counters, the first domain access counter associated with a first compute-memory domain of the compute-memory domains, and relocate the first compute thread to a second compute-memory domain of the compute-memory domains in response to a comparison between a second domain access counter associated with the second compute-memory domain and the first domain access counter.
    Type: Grant
    Filed: June 26, 2021
    Date of Patent: March 11, 2025
    Assignee: INTEL CORPORATION
    Inventors: Rolf Riesen, Robert Wisniewski, Rajesh Poornachandran
  • Publication number: 20240330201
    Abstract: A system and method for address translation in a multi-node computing system. In some embodiments, the system includes a first node. The first node may include: a core; and a global address translation circuit, the core including: a core processing circuit; and a memory management unit configured to map local virtual addresses to global virtual addresses, the global address translation circuit being configured to map global virtual addresses to global physical addresses.
    Type: Application
    Filed: December 8, 2023
    Publication date: October 3, 2024
    Inventors: Alan Gara, Robert Wisniewski, Douglas Joseph, Samantika Sury, Jai Dayal, Rolf Riesen
  • Publication number: 20240311316
    Abstract: A computing node in a multi-node computing system includes a local memory, at least one processor, and an access library. The at least one processor runs an operating system that runs a distributed application in a virtual address space. The application includes a process that generates a first memory access request that includes a first virtual address. The access library is responsive to the first memory access request by: converting the first virtual address into a first physical address, accessing the local memory based on the first physical address including a first indication that the first memory access request is for the local memory, and accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node.
    Type: Application
    Filed: September 14, 2023
    Publication date: September 19, 2024
    Inventors: David LOMBARD, Robert WISNIEWSKI, Douglas JOSEPH, Matthew WOLF, Jai DAYAL, James LOO, Andrew TAUFERNER, Rolf RIESEN
  • Publication number: 20240311289
    Abstract: A method to address memory in nodes of a distributed memory system includes partitioning the memory in each node into one or more memory blocks available for a global memory pool. The method also includes combining, in response to a request to address memory in the global memory pool, a global bit from a global page table with a physical address to generate a global virtual address. The global bit indicates whether the memory is local or remote. The method also includes translating, using global access tuple (GAT) tables, the global virtual address to a global physical address, and addressing a memory block in the global memory pool based on the global physical address.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 19, 2024
    Inventors: David Lombard, Robert Wisniewski, Douglas Joseph, Matthew Wolf, Jai Dayal, James Loo, Andrew Thomas Tauferner, Rolf Riesen
  • Publication number: 20240311315
    Abstract: Systems and methods for computing with multiple nodes. In some embodiments, a method includes: reading, by a first node of a plurality of nodes, from a shared memory shared by the nodes, a first data value; modifying, by the first node, the first data value; storing, by the first node, the modified first data value in a cache of the first node; initiating, by the first node, a global synchronization command; and in response to the initiating, by the first node, of the global synchronization command: indicating, by the first node, that the first node has completed a time step synchronization.
    Type: Application
    Filed: October 9, 2023
    Publication date: September 19, 2024
    Inventors: Alan GARA, Douglas JOSEPH, Arun RODRIGUES, Samantika SURY, Rolf RIESEN, Robert WISNIEWSKI
  • Publication number: 20240311180
    Abstract: A method of migrating threads across a first node running a first operating system and a second node running a second operating system that is a different instance than the first operating system. The method includes a task of receiving, by a thread daemon of the first node, a request from a process on the first node to migrate a thread of the process to the second node. The method also includes a task of sending, by the thread daemon of the first node, the request to a thread daemon of the second node, a task of creating, by the thread daemon of the second node, a thread entry in a thread proxy of the second node and a proxy process on the second node, and a task of instantiating the thread within the proxy process.
    Type: Application
    Filed: November 14, 2023
    Publication date: September 19, 2024
    Inventors: Robert Wisniewski, Rolf Riesen
  • Publication number: 20210326171
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to relocate a compute thread, the apparatus comprising control circuitry to maintain a location of a plurality of domain access counters associated with a plurality of compute-memory domains for a first compute thread, and an execution monitor to set a first domain access counter of the plurality of domain access counters, the first domain access counter associated with a first compute-memory domain of the compute-memory domains, and relocate the first compute thread to a second compute-memory domain of the compute-memory domains in response to a comparison between a second domain access counter associated with the second compute-memory domain and the first domain access counter.
    Type: Application
    Filed: June 26, 2021
    Publication date: October 21, 2021
    Inventors: Rolf Riesen, Robert Wisniewski, Rajesh Poornachandran