Patents by Inventor Rolf Sundblad
Rolf Sundblad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11307635Abstract: A method of controlling operation of a field-powered biometric device comprising biometric acquisition circuitry, processing circuitry controllable to transition between a first functional state having a first power consumption and a second functional state having a second power consumption lower than the first power consumption, and power management circuitry. The method comprises the steps of monitoring, by the power management circuitry, a property indicative of a supply voltage to the processing circuitry; controlling, when the monitored property indicates that the supply voltage has fallen to a first threshold voltage, the processing circuitry to transition from the first functional state to the second functional state; and controlling, when the monitored property indicates that the supply voltage has increased to a second threshold voltage higher than the first threshold voltage, the processing circuitry to transition from the second functional state to the first functional state.Type: GrantFiled: April 24, 2018Date of Patent: April 19, 2022Assignee: FINGERPRINT CARDS ANACATUM IP ABInventors: Peter Almers, David Carling, Rolf Sundblad, Nicholas Weiner, Benjamin Willcocks
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Publication number: 20200064901Abstract: A method of controlling operation of a field-powered biometric device comprising biometric acquisition circuitry, processing circuitry controllable to transition between a first functional state having a first power consumption and a second functional state having a second power consumption lower than the first power consumption, and power management circuitry. The method comprises the steps of monitoring, by the power management circuitry, a property indicative of a supply voltage to the processing circuitry; controlling, when the monitored property indicates that the supply voltage has fallen to a first threshold voltage, the processing circuitry to transition from the first functional state to the second functional state; and controlling, when the monitored property indicates that the supply voltage has increased to a second threshold voltage higher than the first threshold voltage, the processing circuitry to transition from the second functional state to the first functional state.Type: ApplicationFiled: April 24, 2018Publication date: February 27, 2020Applicant: FINGERPRINT CARDS ABInventors: Peter ALMERS, David CARLING, Rolf SUNDBLAD, Nicholas WEINER, Benjamin WILLCOCKS
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Patent number: 9977945Abstract: There is provided a capacitive fingerprint sensing device for sensing a fingerprint pattern of a finger, said capacitive fingerprint sensing device comprising: a protective top layer to be touched by said finger; a first metal layer comprising a two-dimensional array of sensing structures arranged underneath said top layer; a second metal layer, arranged underneath said first metal layer, comprising a plurality of conductive structures a dielectric layer arranged between the first and second metal layers to electrically insulate the first metal layer from the second metal layer, the dielectric layer comprising a low-k material; and readout circuitry arranged underneath said second metal layer and coupled to each of the electrically conductive sensing structures by means of via connections to receive a sensing signal indicative of a distance between said finger and said sensing structure. There is also provided a method for manufacturing such a device.Type: GrantFiled: March 21, 2017Date of Patent: May 22, 2018Assignee: Fingerprint Cards ABInventors: Karl Lundahl, Robert Hägglund, Emil Hjalmarson, Rolf Sundblad, Christer Jansson
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Patent number: 9953204Abstract: A fingerprint sensing system comprising a device connection interface including a device reference potential input, a sensing arrangement, and sensing reference potential providing circuitry. The sensing arrangement includes multiple sensing structures and read-out circuitry connected to each of the sensing structures.Type: GrantFiled: January 5, 2017Date of Patent: April 24, 2018Assignee: FINGERPRINT CARDS ABInventors: Rolf Sundblad, Emil Hjalmarson, Erik Säll, Allan Olsson, Klaas-Jan De Langen
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Publication number: 20170351895Abstract: There is provided a capacitive fingerprint sensing device for sensing a fingerprint pattern of a finger, said capacitive fingerprint sensing device comprising: a protective top layer to be touched by said finger; a first metal layer comprising a two-dimensional array of sensing structures arranged underneath said top layer; a second metal layer, arranged underneath said first metal layer, comprising a plurality of conductive structures a dielectric layer arranged between the first and second metal layers to electrically insulate the first metal layer from the second metal layer, the dielectric layer comprising a low-k material; and readout circuitry arranged underneath said second metal layer and coupled to each of the electrically conductive sensing structures by means of via connections to receive a sensing signal indicative of a distance between said finger and said sensing structure. There is also provided a method for manufacturing such a device.Type: ApplicationFiled: March 21, 2017Publication date: December 7, 2017Inventors: Karl Lundahl, Robert Hägglund, Emil Hjalmarson, Rolf Sundblad, Christer Jansson
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Publication number: 20170308730Abstract: A fingerprint sensing system comprising a device connection interface including a device reference potential input, a sensing arrangement, and sensing reference potential providing circuitry. The sensing arrangement includes multiple sensing structures and read-out circuitry connected to each of the sensing structures.Type: ApplicationFiled: January 5, 2017Publication date: October 26, 2017Inventors: Rolf Sundblad, Emil Hjalmarson, Erik Säll, Allan Olsson, Klaas-Jan De Langen
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Patent number: 9602123Abstract: A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.Type: GrantFiled: December 3, 2014Date of Patent: March 21, 2017Assignees: ANATACUM DESIGN AB, FINGERPRINT CARDS ABInventors: Rolf Sundblad, Staffan Holmbring, Robert Hägglund, Emil Hjalmarsson
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Publication number: 20160322984Abstract: A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port is disclosed. The cognitive signal converter comprises an analog-to-digital converter and a cognitive network. The analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal.Type: ApplicationFiled: December 3, 2014Publication date: November 3, 2016Applicants: Anacatum Design AB, Fingerprint Cards ABInventors: Rolf SUNDBLAD, Staffan HOLMBRING, Robert HÄGGLUND, Emil HJALMARSSON
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Patent number: 9350374Abstract: A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Ni, of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein Ni?1 and ?i=1L Ni?N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Ni, constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.Type: GrantFiled: March 7, 2014Date of Patent: May 24, 2016Assignee: ANACATUM DESIGN ABInventors: Rolf Sundblad, Robert Hägglund, Staffan Holmbring
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Patent number: 9331708Abstract: A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.Type: GrantFiled: March 7, 2014Date of Patent: May 3, 2016Assignee: ANACATUM DESIGN ABInventor: Rolf Sundblad
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Patent number: 9270292Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.Type: GrantFiled: March 7, 2014Date of Patent: February 23, 2016Assignee: ANACATUM DESIGN ABInventors: Rolf Sundblad, Emil Hjalmarsson
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Publication number: 20160020777Abstract: A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N>L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number Ni of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein Ni?1 and ?i=1L Ni?N), and cause each sample of the analog input signal to be digitized in a respective one of the selected Ni constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.Type: ApplicationFiled: March 7, 2014Publication date: January 21, 2016Applicant: ANACATUM DESIGN ABInventors: Rolf SUNDBLAD, Robert HÄGGLUND, Staffan HOLMBRING
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Publication number: 20160006447Abstract: A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.Type: ApplicationFiled: March 7, 2014Publication date: January 7, 2016Applicant: Anacatum Design ABInventor: Rolf SUNDBLAD
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Publication number: 20150381195Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.Type: ApplicationFiled: March 7, 2014Publication date: December 31, 2015Applicant: Anacatum Design ABInventors: Rolf SUNDBLAD, Emil HJALMARSSON
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Patent number: 8576970Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.Type: GrantFiled: September 9, 2009Date of Patent: November 5, 2013Assignee: CSR Technology Inc.Inventors: Graham R. Leach, Gordon A. Wilson, Rolf Sundblad
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Patent number: 8344759Abstract: A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device.Type: GrantFiled: July 10, 2012Date of Patent: January 1, 2013Assignee: CSR Technology Inc.Inventors: Rolf Sundblad, Staffan Gustafsson
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Publication number: 20120280722Abstract: A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device.Type: ApplicationFiled: July 10, 2012Publication date: November 8, 2012Applicant: CSR TECHNOLOGY INC.Inventors: Rolf Sundblad, Staffan Gustafsson
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Patent number: 8222926Abstract: A track and hold circuit (1) comprising a switch device (10) and a capacitive hold device (20). The track and hold circuit (1) comprises a track-voltage generating device (30) adapted to generate a control voltage based on a signal on an input terminal of the switch device (10) and supply the control voltage to the switch device (10) during track phases of the track and hold circuit (1). The control voltage provides a channel charge, which is the same for each track phase, in the switch device (10).Type: GrantFiled: January 18, 2007Date of Patent: July 17, 2012Assignee: CSR Technology Inc.Inventors: Rolf Sundblad, Staffan Gustafsson
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Patent number: 8212697Abstract: An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.Type: GrantFiled: June 15, 2010Date of Patent: July 3, 2012Assignee: CSR Technology Inc.Inventors: Christer Jansson, Rolf Sundblad
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Publication number: 20110304489Abstract: An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.Type: ApplicationFiled: June 15, 2010Publication date: December 15, 2011Applicant: ZORAN CORPORATIONInventors: Jansson Christer, Rolf SUNDBLAD