Abstract: A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area.

Abstract: In accordance with an embodiment, a method includes receiving by a drive circuit electrical power from a voltage tap of a first rectifier circuit that includes a load path and a voltage tap, and using the electrical power by the drive circuit to drive a second rectifier circuit that includes a load path. The load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common circuit node.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

Abstract: A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

Abstract: A semiconductor device includes a buried doped region at a first distance to a main surface of a semiconductor body. A contact structure extends from the main surface to the doped region. The contact structure includes a contact layer formed from a metal-semiconductor alloy that directly adjoins the doped region. The contact structure further includes a fill structure formed from a metal or a conductive metal compound. An insulator structure surrounds the contact structure in cross-sections parallel to the main surface.

Abstract: A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A battery element includes a substrate with a plurality of trenches extending into the substrate. At least a part of each trench of the plurality of trenches is filled with a solid state battery structure. Further, the battery element includes a front side battery element electrode arranged at a front side of the substrate and electrically connected to a first electrode layer of the solid state battery structures within the plurality of trenches. Additionally, the battery element includes a backside battery element electrode arranged at a backside of the substrate and electrically connected to a second electrode layer of the solid state battery structures within the plurality of trenches.

Abstract: A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

Abstract: A power converter circuit includes an input and an output. A supply circuit is configured to receive an input signal from the input and to generate a number of supply signals from the input signal. A number of converter units are provided. Each of the plurality of converter units is configured to receive one of the plurality of supply signals and to output an output signal to the output.

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

Abstract: A semiconductor device is described that includes a transistor chain which is configured as a stacked switch device that switches on and off in response to a drive voltage. The transistor chain includes a first transistor connected in series to a plurality of second transistors. Each transistor in the transistor chain is located at a particular position in the transistor chain according to at least one of a respective capacitance of the transistor and a respective threshold voltage of the transistor.

Abstract: A semiconductor device includes a first region of a first conductivity type and a body region of a second conductivity type, the first conductivity type being different from the second conductivity type. The body region is disposed on a side of a first surface of the semiconductor substrate. The semiconductor device further includes a plurality of trenches arranged in the first surface of the substrate, the trenches extending in a first direction having a component perpendicular to the first surface. Doped portions of the second conductivity type are adjacent to a lower portion of a sidewall of the trenches. The doped portions are electrically coupled to the body region via contact regions. The semiconductor device further includes a gate electrode disposed in an upper portion of the trenches.

Abstract: A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins.

Abstract: A semiconductor component includes semiconductor fins formed between a base plane and a main surface of a semiconductor body. Each semiconductor fin includes a source region formed between the main surface and a channel/body region, and a drift zone formed between the channel/body region and the base plane. The semiconductor component further includes gate electrode structures on two mutually opposite sides of each channel/body region, and a field electrode structure between mutually adjacent ones of the semiconductor fins. Each field electrode structure is separated from the drift zone by a field dielectric and extends from the main surface as far as the base plane. The gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from two sides.

Abstract: An integrated circuit includes a semiconductor body with a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer. The integrated circuit further includes a plurality of transistors each including a load path and a control node The load paths are connected in series, and the plurality of transistors are at least partially integrated in the second semiconductor layer. A voltage limiting structure is connected in parallel with the load path of one of the plurality of transistors, wherein the voltage limiting structure is integrated in the first semiconductor layer and is connected to the one of the plurality of transistors through two electrically conducting vias extending through the insulation layer.

Abstract: A method in a switched-mode power supply (SMPS) and SMPS circuits are provided. The method and circuits use bang-bang regulation to provide for an auxiliary power supply that can be used to power a controller of the SMPS. The additional circuitry required to achieve the method and circuits is minimal and represents advantages over techniques that require an additional power supply or require an auxiliary winding in a transformer. The bang-bang regulation controls switch devices within the SMPS such that a normally-on switch device is enabled while a normally-off switch device is disabled for some period of time. During this period, current is supplied to the SMPS controller and an associated energy-storage device.

Abstract: A layer stack is formed on a main surface of a semiconductor layer, wherein the layer stack includes a dielectric capping layer and a metal layer between the capping layer and the semiconductor layer. Second portions of the layer stack are removed to form gaps between remnant first portions. Adjustment structures of a second dielectric material are formed in the gaps. An interlayer of the first or a third dielectric material is formed that covers the adjustment structures and the first portions. Contact trenches are formed that extend through the interlayer and the capping layer to metal structures formed from remnant portions of the metal layer in the first portions, wherein the capping layer is etched selectively against the auxiliary structures.

Abstract: A semiconductor device includes a semiconductor substrate having a first side. At least a first doping region is formed in the semiconductor substrate. The first doping region has a laterally varying doping dosage and/or a laterally varying implantation depth.