Abstract: Digitized FM signals are fed to a sample-and-hold circuit followed by a first sampling stage which is clocked by a second sampling signal whose frequency is an integral multiple of the frequency of a first sampling signal. The output of the first sampling stage is coupled to the input of an interpolating filter which is clocked by the second sampling signal, and whose output is sampled in a second sampling stage clocked by the second sampling signal. The output of the second sampling stage is coupled to the inputs of two zero-crossing detectors each of which drives a group-delay-controlled monostable multivibrator. The output signals of the latter are added with an average-value compensation signal in an adder whose output is sampled in a third sampling stage clocked by the second sampling signal, and fed to a digital conversion filter clocked by the first and second sampling signals and a third sampling signal.