Abstract: In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

Abstract: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.

Abstract: Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Abstract: Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Abstract: A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data bit order between the memory device and the chip carrier is required.

Abstract: In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

Abstract: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.

Abstract: Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive multiple packets of data to be transmitted to another device over a bus connecting the devices. The comparison circuit may compare the multiple packets of data and select a DBI mode of operation that conserves power and reduces noise on the bus.

Abstract: Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Abstract: Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Abstract: Embodiments of the invention provide a method and apparatus for initializing a computer system, wherein the computer system includes a processor, a volatile memory, and a non-volatile memory. In one embodiment, the method includes, when the computer system is initialized, automatically copying initialization code stored in the non-volatile memory to the volatile memory, wherein circuitry in the volatile memory automatically creates the copy, and executing, by the processor, the copy of the initialization code from the volatile memory.

Abstract: Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a shared interface. In one embodiment, the method includes selecting one of the non-volatile memory controller and the volatile memory via shared control signals of the shared interface, wherein the shared control signals are issued to the non-volatile memory controller and the volatile memory. The method also includes issuing commands to the selected one of the non-volatile memory controller and the volatile memory via the shared control signals.

Abstract: Embodiments of the invention provide a method, devices, and system for accessing data in a nonvolatile memory device via a volatile memory device. In one embodiment, the method includes configuring a size and a base address of an overlay window within an address space of the volatile memory device. The overlay window includes a range of memory addresses. The method also includes receiving an access command via a volatile memory interface of the volatile memory device and using the access command to access a memory array of the volatile memory device if an address of the access command is outside of the overlay window. The method further includes using the access command to access the nonvolatile memory device via a nonvolatile memory interface of the volatile memory device if the address of the access command is within the overlay window.

Abstract: A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data bit order between the memory device and the chip carrier is required.

Abstract: Methods and apparatus for controlling a shared bus. The shared bus is shared between a volatile memory device via a nonvolatile memory interface of the volatile memory and two or more nonvolatile memory controllers. In one embodiment, a method includes receiving a request from a first nonvolatile memory controller of the two or more nonvolatile memory controllers for control of the shared bus. In response to receiving the request, control of the shared bus is granted to the first nonvolatile memory controller if the priority for each of the two or more nonvolatile memory controllers indicates that control should be granted. When control is granted to the first nonvolatile memory controller, the first nonvolatile memory controller is the only nonvolatile memory controller of the two or more nonvolatile memory controllers which performs data access operations via the shared bus.

Abstract: A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data received at a corresponding time, and detecting a first time region during which the data is received. The method also includes using the detected first time region to determine a second time region during which the data may be read using the second clock signal and reading the data using a second clock signal during the second time region.

Abstract: Embodiments of the invention provide a method, devices, and system for issuing commands from a first device to a second device. In one embodiment, the method includes receiving, by the first device, a first command which writes a second command to a memory location within the first device. The second command includes a command code, a first value identifying an operand offset for operands of the second command, and a second value identifying a number of the operands of the second command. The method also includes providing the second command to the second device. In one embodiment, the second device loads the operands of the second command using the offset and the number provided by the second command.

Abstract: Embodiments of the invention generally provide a method for configuring an overlay window in a volatile memory device. In one embodiment, the method includes receiving a first command which provides at least a portion of a base address for the overlay window, wherein the overlay window comprises a range of memory addresses, and receiving a second command which provides a size of the overlay window. An access command received by the volatile memory device is used to access a memory array of the volatile memory device if an address of the access command is outside of the overlay window. The access command received by the volatile memory device is used to access a memory location outside of the memory array if the address of the access command is within the overlay window.

Abstract: Embodiments of the invention provide a method, devices, and system for accessing remote control registers in a remote device via a volatile memory device. In one embodiment, the method includes receiving, by the volatile memory device via a volatile memory interface, a write command updating mirrored control registers within the volatile memory device. The method also includes transferring the mirrored control registers from the volatile memory device to the remote control registers in the remote device via a second interface. In one embodiment, the remote control registers comprise one of Universal Serial Bus (USB) registers and Advanced Technology Attachment (ATA) registers.

Abstract: Embodiments of the invention provide a method, devices, and system for accessing data in a nonvolatile memory device via a volatile memory device. In one embodiment, the method includes configuring a size and a base address of an overlay window within an address space of the volatile memory device. The overlay window includes a range of memory addresses. The method also includes receiving an access command via a volatile memory interface of the volatile memory device and using the access command to access a memory array of the volatile memory device if an address of the access command is outside of the overlay window. The method further includes using the access command to access the nonvolatile memory device via a nonvolatile memory interface of the volatile memory device if the address of the access command is within the overlay window.