Abstract: Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of accelerator cores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one or more fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU).

Abstract: In one embodiment a processor comprises logic to determine a center of mass of a plurality of data dependencies associated with a task and assign the task to a processor in the system which is closest to the center of mass. Other embodiments may be described.

Abstract: In a method of dynamically changing a computation performed by an application executing on a digital computer, the application is characterized in terms of slack and workloads of underlying components of the application and of interactions therebetween. The application is enhanced dynamically based on predictive models generated from the characterizing action and on the dynamic availability of computational resources. Strictness of data consistency constraints is adjusted dynamically between threads in the application, thereby providing runtime control mechanisms for dynamically enhancing the application.