Patents by Inventor Romain Esteve
Romain Esteve has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250113592Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a semiconductor body including a first doped region of a first conductivity type and a second doped region of a second conductivity type. The semiconductor device may include a metal structure, in the semiconductor body, overlying the second doped region. The metal structure may include a first sidewall adjacent a first portion of the first doped region, a second sidewall adjacent a second portion of the first doped region, and a third sidewall adjacent the second doped region. The semiconductor device may include a Schottky contact including a junction of the third sidewall of the metal structure with the second doped region.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Ravi Keshav JOSHI, Fabian RASINGER, Kristijan Luka MLETSCHNIG, Romain ESTEVE, Caspar LEENDERTZ
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Patent number: 11901407Abstract: A semiconductor device having an improved junction termination extension region is provided. The disclosure particularly relates to diodes having such an improved junction termination extension. The semiconductor device includes an active area extending in a first direction, and a junction termination extension, ‘JTE’, region of a first charge type surrounding the active area. The JTE region includes a plurality of field relief sub-regions that each surround the active area and that are mutually spaced apart in a direction perpendicular to a circumference of the active area. The plurality of field relief sub-regions includes a first group of field relief sub-regions, and for each field relief sub-region of the first group, a plurality of field relief elements of a second charge type is provided therein, which field relief elements are mutually spaced apart in a circumferential direction with respect to the active area.Type: GrantFiled: September 24, 2021Date of Patent: February 13, 2024Assignee: Nexperia B.VInventors: Romain Esteve, Tim Böttcher
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Patent number: 11881512Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.Type: GrantFiled: November 4, 2021Date of Patent: January 23, 2024Assignee: Infineon Technologies AGInventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
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Publication number: 20230402550Abstract: A vertical semiconductor component including: a substrate; an epitaxial layer doped with a first conductivity type, preferably n-doped, provided on the substrate; a metal layer deposited on the epitaxial layer to form a Schottky contact with the epitaxial layer; a plurality of first regions embedded in the epitaxial layer and contacting the metal layer, and doped with a second conductivity type, in order to form a plurality of pn-junctions with the epitaxial layer; and a plurality of second regions embedded in a first region and contacting the metal layer, and doped with a second conductivity type, at a higher concentration, in order to form a plurality of low-resistance ohmic contacts with the metal layer. The semiconductor component includes a lateral cross section along which there are more first regions than second regions.Type: ApplicationFiled: June 9, 2023Publication date: December 14, 2023Applicant: NEXPERIA B.V.Inventors: Tim BÖTTCHER, Sönke HABENICHT, Romain ESTEVE
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Patent number: 11842938Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: GrantFiled: November 30, 2021Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 11764063Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.Type: GrantFiled: May 28, 2020Date of Patent: September 19, 2023Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Romain Esteve, Moriz Jelinek, Caspar Leendertz, Werner Schustereder
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Publication number: 20230238442Abstract: A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.Type: ApplicationFiled: January 17, 2023Publication date: July 27, 2023Inventors: Ravi Keshav JOSHI, Romain ESTEVE, Saurabh ROY, Bernhard GOLLER, Werner SCHUSTEREDER, Kristijan Luka MLETSCHNIG
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Patent number: 11626477Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.Type: GrantFiled: July 14, 2021Date of Patent: April 11, 2023Assignee: Infineon Technologies AGInventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
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Patent number: 11552172Abstract: First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.Type: GrantFiled: July 11, 2020Date of Patent: January 10, 2023Assignee: Infineon Technologies AGInventors: Caspar Leendertz, Romain Esteve, Moriz Jelinek, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
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Patent number: 11462611Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.Type: GrantFiled: December 4, 2020Date of Patent: October 4, 2022Assignee: Infineon Technologies AGInventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
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Patent number: 11380756Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.Type: GrantFiled: January 3, 2020Date of Patent: July 5, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Caspar Leendertz, Rudolf Elpelt, Romain Esteve, Thomas Ganner, Jens Peter Konrath, Larissa Wehrhahn-Kilian
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Publication number: 20220102486Abstract: A semiconductor device having an improved junction termination extension region is provided. The disclosure particularly relates to diodes having such an improved junction termination extension. The semiconductor device includes an active area extending in a first direction, and a junction termination extension, ‘JTE’, region of a first charge type surrounding the active area. The JTE region includes a plurality of field relief sub-regions that each surround the active area and that are mutually spaced apart in a direction perpendicular to a circumference of the active area. The plurality of field relief sub-regions includes a first group of field relief sub-regions, and for each field relief sub-region of the first group, a plurality of field relief elements of a second charge type is provided therein, which field relief elements are mutually spaced apart in a circumferential direction with respect to the active area.Type: ApplicationFiled: September 24, 2021Publication date: March 31, 2022Applicant: NEXPERIA B.V.Inventors: Romain Esteve, Tim Böttcher
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Publication number: 20220093483Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: ApplicationFiled: November 30, 2021Publication date: March 24, 2022Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20220059659Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
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Patent number: 11217500Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.Type: GrantFiled: April 9, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 11195946Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.Type: GrantFiled: February 10, 2021Date of Patent: December 7, 2021Assignee: Infineon Technologies AGInventors: Andreas Peter Meiser, Romain Esteve, Roland Rupp
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Patent number: 11195921Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.Type: GrantFiled: May 14, 2019Date of Patent: December 7, 2021Assignee: Infineon Technologies AGInventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
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Publication number: 20210343835Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
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Patent number: 11101343Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.Type: GrantFiled: May 6, 2019Date of Patent: August 24, 2021Assignee: Infineon Technologies AGInventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
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Publication number: 20210167203Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.Type: ApplicationFiled: February 10, 2021Publication date: June 3, 2021Inventors: Andreas Peter Meiser, Romain Esteve, Roland Rupp