Patents by Inventor Romain Gwoziecki

Romain Gwoziecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290633
    Abstract: A method for producing, on a structure based on a material III-V, of a dielectric layer, the method comprising producing a first dielectric film by ALD by carrying out a plurality of first cycles, each comprising at least: one injection in the reaction chamber of a precursor based on a first material and one injection in the reaction chamber of a water or ozone-based precursor; and producing, on the first dielectric film, a second dielectric film by plasma-enhanced ALD by carrying out a plurality of second cycles, each comprising at least: one injection in the reaction chamber of a precursor based on a second material and one injection in the reaction chamber of an oxygen or nitrogen based precursor.
    Type: Application
    Filed: July 8, 2021
    Publication date: September 14, 2023
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE GRENOBLE ALPES
    Inventors: Maxime LEGALLAIS, Bassem SALEM, Thierry BARON, Romain GWOZIECKI, Marc PLISSONNIER
  • Publication number: 20230111123
    Abstract: A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage Vbias_substrate may be applied to the substrate.
    Type: Application
    Filed: February 25, 2021
    Publication date: April 13, 2023
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE GRENOBLE ALPES
    Inventors: Maxime LEGALLAIS, Bassem SALEM, Thierry BARON, Romain GWOZIECKI, Marc PLISSONNIER
  • Patent number: 11404628
    Abstract: A voltage transformer including a beam or membrane made of a first polymer material having a resonance frequency in the range from 1 Hz to 1,000 Hz and including on the beam or membrane a stack successively including: a first electrode; a first piezoelectric layer made of a second polymer material; a second electrode; a second piezoelectric layer made of a third polymer material identical to the second polymer material or different from the second polymer material; and a third electrode.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 2, 2022
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Romain Gwoziecki, Marine Galliari, Antoine Latour
  • Patent number: 11251274
    Abstract: A semiconductor device includes a substrate; a semiconductor structure arranged on the substrate, the semiconductor structure including at least one first semiconductor layer; an insulator layer arranged on the semiconductor structure; a field plate covering a part of the insulator layer, wherein the insulator layer includes a non-linear dielectric material having a permittivity that decreases as an electric field traversing the dielectric material increases.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 15, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Romain Gwoziecki, Gwenaël Le Rhun
  • Publication number: 20200152747
    Abstract: A semiconductor device includes a substrate; a semiconductor structure arranged on the substrate, the semiconductor structure including at least one first semiconductor layer; an insulator layer arranged on the semiconductor structure; a field plate covering a part of the insulator layer, wherein the insulator layer includes a non-linear dielectric material having a permittivity that decreases as an electric field traversing the dielectric material increases.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 14, 2020
    Inventors: Romain GWOZIECKI, Gwenaël LE RHUN
  • Publication number: 20180175280
    Abstract: A voltage transformer including a beam or membrane made of a first polymer material having a resonance frequency in the range from 1 Hz to 1,000 Hz and including on the beam or membrane a stack successively including: a first electrode; a first piezoelectric layer made of a second polymer material; a second electrode; a second piezoelectric layer made of a third polymer material identical to the second polymer material or different from the second polymer material; and a third electrode.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 21, 2018
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Romain Gwoziecki, Marine Galliari, Antoine Latour
  • Patent number: 9009637
    Abstract: A method for making a matrix device including a matrix of photodetecting or photoemitting elements, the method including designing operations for: a) identifying, from at least one topology of the matrix device, one or more spurious conducting closed circuits; b) selecting at least one photodetecting or photoemitting element of the matrix device belonging to at least one of the spurious conducting closed circuits identified, the at least one element selected being made inactive.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 14, 2015
    Assignees: Commissariat á l'énergie atomique et aux énergies alternatives, ISORG
    Inventors: Christophe Premont, Romain Gwoziecki
  • Publication number: 20140149959
    Abstract: A method for making a matrix device including a matrix of photodetecting or photoemitting elements, the method including designing operations for: a) identifying, from at least one topology of the matrix device, one or more spurious conducting closed circuits; b) selecting at least one photodetecting or photoemitting element of the matrix device belonging to at least one of the spurious conducting closed circuits identified, the at least one element selected being made inactive.
    Type: Application
    Filed: April 12, 2012
    Publication date: May 29, 2014
    Applicants: ISORG, COMMISSARIAT A l "ENERGIE ATOMQUE ET AUX ENE ALT
    Inventors: Christophe Premont, Romain Gwoziecki
  • Patent number: 8710494
    Abstract: The organic memory device is a double-gate transistor that successively comprises a first gate electrode, a first gate dielectric, an organic semi-conductor material, a second gate dielectric and a second gate electrode. Source and drain electrodes are arranged in the organic semiconductor material and define an inter-electrode surface. A trapping area is arranged between the organic semiconductor material and one of the gate electrodes and is in electric contact with one of the gate electrodes or the organic semi-conductor material. The trapping area is at least facing the inter-electrode surface.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 29, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Romain Gwoziecki, Mohamed Benwadih, Philippe Coronel, Stéphanie Jacob
  • Patent number: 8604482
    Abstract: A microelectronic device includes a plurality of disconnected similar semiconducting portions, electrically isolated from each other and forming a semiconductor layer, at a spacing by a constant distance and with a shape parallel to the other portions. The microelectronic device also includes two electrodes arranged in contact with the semiconductor layer such that a maximum distance separating the two electrodes is less than the largest dimension of one of the semiconductor portions. The shape and dimensions of the semiconductor portions, the spacing between the semiconductor portions, the shape and dimensions of the electrodes and the layout of the electrodes relative to the semiconductor portions are such that at least one of the semiconductor portions electrically connects the two electrodes to each other. The largest dimensions of the semiconductor portions are perpendicular to the largest dimension of the electrodes, the electrodes being similar.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 10, 2013
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Romain Gwoziecki, Romain Coppard
  • Publication number: 20130056834
    Abstract: A microelectronic device includes a plurality of disconnected similar semiconducting portions, electrically isolated from each other and forming a semiconductor layer, at a spacing by a constant distance and with a shape parallel to the other portions. The microelectronic device also includes two electrodes arranged in contact with the semiconductor layer such that a maximum distance separating the two electrodes is less than the largest dimension of one of the semiconductor portions. The shape and dimensions of the semiconductor portions, the spacing between the semiconductor portions, the shape and dimensions of the electrodes and the layout of the electrodes relative to the semiconductor portions are such that at least one of the semiconductor portions electrically connects the two electrodes to each other. The largest dimensions of the semiconductor portions are perpendicular to the largest dimension of the electrodes, the electrodes being similar.
    Type: Application
    Filed: May 3, 2011
    Publication date: March 7, 2013
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Romain Gwoziecki, Romain Coppard
  • Publication number: 20120199821
    Abstract: The organic memory device is a double-gate transistor that successively comprises a first gate electrode, a first gate dielectric, an organic semi-conductor material, a second gate dielectric and a second gate electrode. Source and drain electrodes are arranged in the organic semiconductor material and define an inter-electrode surface. A trapping area is arranged between the organic semiconductor material and one of the gate electrodes and is in electric contact with one of the gate electrodes or the organic semi-conductor material. The trapping area is at least facing the inter-electrode surface.
    Type: Application
    Filed: September 30, 2010
    Publication date: August 9, 2012
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Romain Gwoziecki, Mohamed Benwadih, Philippe Coronel, Stephanie Jacob
  • Patent number: 6667513
    Abstract: A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: December 23, 2003
    Assignee: France Télécom
    Inventors: Thomas Skotnicki, Romain Gwoziecki
  • Patent number: RE41764
    Abstract: A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: September 28, 2010
    Inventors: Thomas Skotnicki, Romain Gwoziecki