Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

Abstract: A voltage scaling system can scale a supply voltage while preventing a processor from communicating with first system components that are rendered unstable from the scaling. On the other hand, the voltage scaling system allows second system components that are stable during the scaling to communicate with the processor. A processor scales a system supply voltage to a target supply voltage. The processor halts operations of the first system components and executes the instruction. When the first system components are halted, the processor cannot access the first system components. The second system components can continue operating during the scaling. A controller that saves power can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an indication to a power management unit, after which the first system components continue to operate.

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

Abstract: A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

Abstract: A microcontroller includes first and second modules. The first module can operate in a mode that causes interference with operation of the second module. A control circuit on the first module and a control circuit on the second module coordinate operation of the first and second modules to prevent the interference from causing the second module to function incorrectly.

Abstract: A microcontroller includes first and second modules. The first module can operate in a mode that causes interference with operation of the second module. A control circuit on the first module and a control circuit on the second module coordinate operation of the first and second modules to prevent the interference from causing the second module to function incorrectly.