Patents by Inventor Roman A. Royer
Roman A. Royer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11605416Abstract: Methods, systems, and devices for reducing duty cycle degradation for a signal path are described. In some examples, a memory system may alternate a polarity of a signal line or signal path that includes a set of transistors during successive active periods of the memory system. In some cases, the memory device may include an inversion control component configured to operate the signal using either a first polarity or a second polarity. The inversion control component may receive an indication when the memory system enters an active period, and may accordingly alternate or the polarity of the signal path during successive active periods. In some examples, the signal path may be coupled with one or more output components which may uninvert signals from the signal path when the inversion control component has inverted the polarity of the signal path.Type: GrantFiled: November 10, 2021Date of Patent: March 14, 2023Assignee: Micron Technology, Inc.Inventor: Roman A. Royer
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Patent number: 11581056Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.Type: GrantFiled: December 16, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Chikara Kondo, Roman A. Royer
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Publication number: 20210182065Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for in-line no operation (NOP) repeat commands. An algorithmic pattern generator (APG) may be loaded with a set of instructions. A line of the instructions may include an active command and an NOP repeat command. The active command may be a command to be provided by the APG when the line of instruction is executed. The NOP repeat command may be a value which indicates a number of times that an NOP command should be issued after the active command when the line of instruction is executed. The APG may include an NOP controller circuit (and/or phase controller circuit) which determines when the next active command should be provided based, in part, on a count of the number of times that an NOP command is issued.Type: ApplicationFiled: December 16, 2019Publication date: June 17, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Chikara Kondo, Roman A. Royer
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Publication number: 20210104293Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Chiaki Dono, Chikara Kondo, Roman A. Royer
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Patent number: 10937518Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples.Type: GrantFiled: December 12, 2018Date of Patent: March 2, 2021Assignee: Micron Technology, Inc.Inventors: Roman A. Royer, Chikara Kondo, Chiaki Dono
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Patent number: 10896738Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.Type: GrantFiled: October 2, 2019Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Chikara Kondo, Roman A. Royer
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Publication number: 20200194090Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Roman A. Royer, Chikara Kondo, Chiaki Dono
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Patent number: 8879340Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed.Type: GrantFiled: October 18, 2010Date of Patent: November 4, 2014Assignee: Round Rock Research, LLCInventor: Roman Royer
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Publication number: 20110069567Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed.Type: ApplicationFiled: October 18, 2010Publication date: March 24, 2011Applicant: Round Rock Research, LLCInventor: Roman Royer
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Patent number: 7817482Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed.Type: GrantFiled: August 29, 2008Date of Patent: October 19, 2010Assignee: Round Rock Research, LLCInventor: Roman Royer
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Publication number: 20080316841Abstract: A memory device has multiple bi-directional data paths. One of the multiple bidirectional data paths is configured to transfer data at one speed. Another one of the multiple bidirectional data paths is configured to transfer data at another speed.Type: ApplicationFiled: August 29, 2008Publication date: December 25, 2008Inventor: Roman Royer
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Patent number: 7423918Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory device has different modes. Depending on a certain mode, the memory device uses different combinations of the multiple bi-directional data paths to transfer data either at a single speed or at multiple speeds. In some cases, the data represents data information to be stored in memory cells of the memory device. In other cases, the data represents control information and feedback information to be transferred to and from internal circuits, besides the memory cells, of the memory device.Type: GrantFiled: December 28, 2004Date of Patent: September 9, 2008Assignee: Micron Technology, Inc.Inventor: Roman Royer
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Patent number: 6961269Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory device has different modes. Depending on a certain mode, the memory device uses different combinations of the multiple bi-directional data paths to transfer data either at a single speed or at multiple speeds. In some cases, the data represents data information to be stored in memory cells of the memory device. In other cases, the data represents control information and feedback information to be transferred to and from internal circuits, besides the memory cells, of the memory device.Type: GrantFiled: June 24, 2003Date of Patent: November 1, 2005Assignee: Micron Technology, Inc.Inventor: Roman Royer
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Publication number: 20040264255Abstract: A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory device has different modes. Depending on a certain mode, the memory device uses different combinations of the multiple bi-directional data paths to transfer data either at a single speed or at multiple speeds. In some cases, the data represents data information to be stored in memory cells of the memory device. In other cases, the data represents control information and feedback information to be transferred to and from internal circuits, besides the memory cells, of the memory device.Type: ApplicationFiled: June 24, 2003Publication date: December 30, 2004Applicant: Micron Technology, Inc.Inventor: Roman Royer