Abstract: A computer-implemented method, according to one embodiment, is for selectively storing parity data in different types of memory which include a higher performance memory and a lower performance memory. The computer-implemented method includes: receiving a write request, and determining whether the write request includes parity data. In response to determining that the write request includes parity data, a determination is made as to whether a write heat of the parity data is in a predetermined range. In response to determining that that write heat of the parity data is in the predetermined range, another determination is made as to whether the parity data has been read since a last time the parity data was updated. Furthermore, in response to determining that the parity data has been read since a last time the parity data was updated, the parity data is stored in the higher performance memory.

Abstract: A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Abstract: A computer-implemented method, according to one embodiment, is for managing a plurality of blocks of memory in two or more pools. The computer-implemented method includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in single-level cell (SLC) mode. A second subset of the plurality of blocks is also maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. Current workload input/output (I/O) metrics are also identified during runtime. Moreover, a size of the first subset of blocks in the first pool and a size of the second subset of blocks in the second pool are adjusted based on the current workload I/O metrics.

Abstract: A memory controller for recovering data due to transient effects of nonvolatile memory is provided. A memory controller receives a read request for a page stored in the nonvolatile memory. The memory controller issues a first read command. The memory controller records a time stamp for the first read command. In response to a failure during the first read command, the memory controller waits for a delay after the recorded time stamp and the memory controller issues a second read command to the page, wherein the second read command applies a read voltage offset that is dependent on the delay between the first read command and the second read command and at least one other parameter.

Abstract: A RAID controller periodically collects an indication of a current compression ratio achieved by each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the current compression ratio. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.

Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.

Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

Abstract: A non-volatile memory includes a plurality of physical blocks of storage each including a respective plurality of cells, where each of the plurality of cells is individually capable of storing multiple bits of data. A controller assigns physical blocks among the plurality of physical blocks to a first pool containing physical blocks operating in a first (e.g., QLC) mode for storing a greater number of bits per cell and assigns other physical blocks among the plurality of physical blocks to a second pool containing physical blocks operating in a second (e.g., SLC) mode for storing a lesser number of bits per cell. The controller transfers physical blocks between the first pool and the second pool based on at least bit error rates measured for the transferred physical blocks.

Abstract: Embodiments for adaptive placement of parity information within Redundant Array of Independent Disks (RAID) stripes in a computer storage environment. A RAID controller periodically collects a physical capacity usage of each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the physical capacity usage. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.

Abstract: A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.

Abstract: A method of managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithm—e.g., a first programming pass and a second programming pass—for programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.

Abstract: A method for intra-block recovery of an Erasure Code protected memory page stripe may be provided. The method comprises providing a data storage device comprising a plurality of EC protected memory page stripes, each of which comprising a plurality of memory pages, wherein corresponding memory pages of the plurality of the page stripes are organized as a plurality of blocks comprising each the corresponding pages, each memory page comprising a plurality of non-volatile memory cells, and wherein each page stripe comprises at least one stripe parity page, grouping memory pages of a block into at least one window, each window comprising a plurality of memory pages of the block, and maintaining at least one parity page for each window of the block, such that a page read failure is recoverable even if multiple memory pages per page stripe experience a read failure concurrently.

Abstract: A computer-implemented method, according to one embodiment, is for maintaining heat information of data while in a cache. The computer-implemented method includes: transferring data from non-volatile memory to the cache, such that the data is stored in a first page in the cache. Previous read and/or write heat information associated with the data is maintained by preserving one or more bits in a hash table which correspond to the data in the first page. Moreover, the data is destaged from the first page in the cache to the non-volatile memory, and the one or more bits in the hash table which correspond to the data are updated to reflect current read and/or write heat information associated with the data.

Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.

Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a block switching metric for each block of memory in the storage system. A determination is made as to whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block. In response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, the first block is erased. The first block is then transferred from the first pool to a second RTU queue which corresponds to the second pool. A second block in the second pool is also erased and transferred from the second pool to a first RTU queue which corresponds to the first pool.

Abstract: A non-volatile memory includes a plurality of physical blocks of storage each including a respective plurality of cells, where each of the plurality of cells is individually capable of storing multiple bits of data. A controller assigns physical blocks among the plurality of physical blocks to a first pool containing physical blocks operating in a first (e.g., QLC) mode for storing a greater number of bits per cell and assigns other physical blocks among the plurality of physical blocks to a second pool containing physical blocks operating in a second (e.g., SLC) mode for storing a lesser number of bits per cell. The controller transfers physical blocks between the first pool and the second pool based on at least bit error rates measured for the transferred physical blocks.

Abstract: A method of managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithm—e.g., a first programming pass and a second programming pass—for programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.

Abstract: Embodiments for adaptive placement of parity information within Redundant Array of Independent Disks (RAID) stripes in a computer storage environment. A RAID controller periodically collects a physical capacity usage of each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the physical capacity usage. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.