Patents by Inventor Roman Lutchyn
Roman Lutchyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11877523Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.Type: GrantFiled: July 7, 2021Date of Patent: January 16, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Michael Freedman, Andrey Antipov
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Publication number: 20230309418Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.Type: ApplicationFiled: May 5, 2023Publication date: September 28, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
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Patent number: 11707000Abstract: A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.Type: GrantFiled: June 27, 2018Date of Patent: July 18, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Dmitry Pikulin, Michael H. Freedman, Roman Lutchyn, Peter Krogstrup Jeppesen, Parsa Bonderson
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Patent number: 11696516Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.Type: GrantFiled: September 11, 2020Date of Patent: July 4, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
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Publication number: 20210336119Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.Type: ApplicationFiled: July 7, 2021Publication date: October 28, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Michael Freedman, Andrey Antipov
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Patent number: 11081634Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.Type: GrantFiled: June 29, 2018Date of Patent: August 3, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Michael Freedman, Andrey Antipov
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Patent number: 11056634Abstract: Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction.Type: GrantFiled: December 16, 2019Date of Patent: July 6, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Andrey Antipov
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Publication number: 20210184094Abstract: Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction.Type: ApplicationFiled: December 16, 2019Publication date: June 17, 2021Inventors: Roman Lutchyn, Andrey Antipov
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Publication number: 20210005661Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.Type: ApplicationFiled: September 11, 2020Publication date: January 7, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
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Patent number: 10777605Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological obit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing, architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.Type: GrantFiled: November 11, 2019Date of Patent: September 15, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
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Publication number: 20200287120Abstract: The disclosure concerns fabricating a quantum device. In an embodiment, a method is disclosed comprising: providing a substrate and an insulator formed on the substrate; from combinations of selective-area-grown semiconductor material along with regions of a superconducting material, forming a network of nanowires oriented in a plane of the substrate which can be used to produce a Majorana-based topological qubit; and fabricating a side gate for controlling a topological segment of the qubit; wherein the selective-area-grown semiconductor material is grown on the substrate, by etching trenches in the insulator formed on the substrate to define the nanowires and depositing the semiconductor material in the trenches defining the nanowires; and wherein the fabricating of the side gate comprises etching the dielectric to create a trench for the side gate and depositing the side gate in the trench for the side gate.Type: ApplicationFiled: June 27, 2018Publication date: September 10, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Dmitry Pikulin, Michael H. Freedman, Roman Lutchyn, Peter Krogstrup Jeppesen, Parsa Bonderson
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Patent number: 10692010Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.Type: GrantFiled: September 3, 2018Date of Patent: June 23, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas
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Patent number: 10665701Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.Type: GrantFiled: September 3, 2018Date of Patent: May 26, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekėnas
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Patent number: 10635988Abstract: Embodiments of the disclosed technology comprise methods and/or devices for performing measurements and/or manipulations of the collective state of a set of Majorana quasiparticles/Majorana zero modes (MZMs). Example methods/devices utilize the shift of the combined energy levels due to coupling multiple quantum systems (e.g., in a Stark-effect-like fashion). The example methods can be used for performing measurements of the collective topological charge or fermion parity of a group of MZMs (e.g., a pair of MZMs or a group of 4 MZMs). The example devices can be utilized in any system supporting MZMs.Type: GrantFiled: June 27, 2017Date of Patent: April 28, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Parsa Bonderson, Michael Freedman, Torsten Karzig, Chetan Nayak, Jason Alicea, Christina Knapp
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Publication number: 20200098821Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological obit comprising 6 Majorana zero modes (MZMs) on a mesoscopic super-conducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing, architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.Type: ApplicationFiled: November 11, 2019Publication date: March 26, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
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Publication number: 20200027971Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.Type: ApplicationFiled: September 3, 2018Publication date: January 23, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas
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Publication number: 20200027030Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.Type: ApplicationFiled: September 3, 2018Publication date: January 23, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas
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Patent number: 10490600Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.Type: GrantFiled: June 28, 2017Date of Patent: November 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
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Patent number: 10346348Abstract: Among the embodiments disclosed herein are example methods for generating all Clifford gates for a system of Majorana Tetron qubits (quasiparticle poisoning protected) given the ability to perform certain 4 Majorana zero mode measurements. Also disclosed herein are example designs for scalable quantum computing architectures that enable the methods for generating the Clifford gates, as well as other operations on the states of MZMs. These designs are configured in such a way as to allow the generation of all the Clifford gates with topological protection and non-Clifford gates (e.g. a ?/8-phase gate) without topological protection, thereby producing a computationally universal gate set. Several possible realizations of these architectures are disclosed.Type: GrantFiled: June 28, 2017Date of Patent: July 9, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Matthew Hastings, Torsten Karzig, Parsa Bonderson, Michael Freedman, Roman Lutchyn, Chetan Nayak
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Publication number: 20190013457Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.Type: ApplicationFiled: June 29, 2018Publication date: January 10, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Roman Lutchyn, Michael Freedman, Andrey Antipov