Abstract: An integrated circuit (IC) chip includes a first memory that stores first information, and a second memory that stores second information that it to be protected from unauthorized access. Communication interface circuitry gives a processor external to the IC chip read access and/or write access to components of the IC chip. Embedded hardware security circuitry selectively provides the processor external to the IC chip with secure access to the second memory. Interconnect circuitry i) selectively grants the processor unsecured access to the first memory via the communication interface circuitry, ii) selectively grants the processor access to the embedded hardware security, and iii) limits access to the second memory.

Abstract: Hardware circuitry of a network device in a communication network collects telemetry data generated by the network device, the telemetry data providing information regarding operational status of at least one of i) the network device, and ii) one or more network links connected to the network device. The hardware circuitry generates packets that include respective sets of the telemetry data collected by the hardware circuitry. The packets are addressed to a remote network device in, or communicatively coupled to, the communication network. The hardware circuitry prompts the network device to transmit the packets to the remote network device.

Abstract: An integrated circuit (IC) chip includes a first memory that stores first information, and a second memory that stores second information that it to be protected from unauthorized access. Communication interface circuitry gives a processor external to the IC chip read access and/or write access to components of the IC chip. Embedded hardware security circuitry selectively provides the processor external to the IC chip with secure access to the second memory. Interconnect circuitry i) selectively grants the processor unsecured access to the first memory via the communication interface circuitry, ii) selectively grants the processor access to the embedded hardware security, and iii) limits access to the second memory.

Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.

Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.