Patents by Inventor Roman Nos

Roman Nos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10277511
    Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 30, 2019
    Assignee: NXP USA, Inc.
    Inventors: Shai Koren, Evgeni Ginzburg, Yuval Harari, Adi Katz, Roman Nos
  • Patent number: 9912604
    Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: March 6, 2018
    Assignee: NXP USA, Inc.
    Inventors: Roman Nos, Noam Efrati, Sagi Gurfinkel
  • Publication number: 20170180253
    Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Shai Koren, Evgeni Ginzburg, Yuval Harari, Adi Katz, Roman Nos
  • Publication number: 20170034069
    Abstract: In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Roman Nos, Noam Efrati, Sagi Gurfinkel