Abstract: A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.

Abstract: An improved electrically erasable read only memory (EEPROM) includes a EEPROM cell and a static random access memory (SRAM) cell. Complementary pairs of complementary metal oxide semiconductor (CMOS) transistors connect the gates of transistors forming the EEPROM cell to either the corresponding data nodes of the SRAM cell or to a fixed read or nonzero test voltage. When formed into an array, it is not necessary to replicate differential sense circuitry in every cell. EEPROM transistor pairs are combined into columns which share a common sense latch. The nonsero test voltage allows for measurement of the actual threshold voltages (V.sub.T) of each EEPROM device individually.