Patents by Inventor ROMAN W. OLAC-VAW

ROMAN W. OLAC-VAW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964690
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Nidhi Nidhi, Chen-Guan Lee
  • Publication number: 20210090956
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
  • Patent number: 10950606
    Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Roman W. Olac-Vaw, Chia-Hong Jan
  • Patent number: 10930729
    Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Neville L. Dias, Rahul Ramaswamy, Hsu-Yu Chang, Roman W. Olac-Vaw, Chen-Guan Lee
  • Patent number: 10892192
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Patent number: 10892261
    Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee, Chia-Hong Jan
  • Patent number: 10854757
    Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Hsu-Yu Chang, Chia-Hong Jan, Walid M. Hafez, Neville L. Dias, Roman W. Olac-Vaw, Chen-Guan Lee
  • Patent number: 10784378
    Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee, Chia-Hong Jan, Everett S. Cassidy-Comfort
  • Patent number: 10761264
    Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Chia-Hong Jan, Walid Hafez, Neville Dias, Hsu-Yu Chang, Roman W. Olac-Vaw, Chen-Guan Lee
  • Publication number: 20200273752
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
  • Patent number: 10756210
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Roman W. Olac-Vaw, Chen-Guan Lee
  • Patent number: 10692771
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Publication number: 20200066712
    Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.
    Type: Application
    Filed: September 29, 2016
    Publication date: February 27, 2020
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Joodong PARK, Chen-Guan LEE, Chia-Hong JAN
  • Publication number: 20200066907
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Hsu-Yu CHANG, Neville L. DIAS, Rahul RAMASWAMY, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20200066897
    Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Joodong PARK, Chen-Guan LEE, Chia-Hong JAN, Everett S. CASSIDY-COMFORT
  • Publication number: 20200043914
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: ROMAN W. OLAC-VAW, WALID M. HAFEZ, CHIA-HONG JAN, HSU-YU CHANG, NEVILLE L. DIAS, RAHUL RAMASWAMY, NIDHI NIDHI, CHEN-GUAN LEE
  • Publication number: 20190348516
    Abstract: Disclosed herein are transistor arrangements with one or more FinFETs, where threshold voltage tuning of a given FinFET may be implemented by controlling the height of a work function (WF) material provided as a layer at least partially surrounding sidewalls of the upper-most portion of the fin of that FinFET. In some embodiments, such a control may be achieved as a part of forming a gate stack of a FinFET. In particular, a layer of a desired WF material may be deposited within an opening formed around a channel region of a fin as a part of forming the gate stack, and subsequently recessed to a desired height, where, for a given geometry and materials selection, the amount of WF material recess controls threshold voltage of the resulting FinFET. In this manner, different FinFETs in a single transistor arrangement may have different heights of their WF material layer.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Intel Corporation
    Inventors: Rahul Ramaswamy, Walid M. Hafez, Roman W. Olac-vaw
  • Publication number: 20190287972
    Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.
    Type: Application
    Filed: September 30, 2016
    Publication date: September 19, 2019
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Chia-Hong JAN
  • Publication number: 20190278022
    Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.
    Type: Application
    Filed: December 30, 2016
    Publication date: September 12, 2019
    Inventors: Rahul RAMASWAMY, Chia-Hong JAN, Walid HAFEZ, Neville DIAS, Hsu-Yu CHANG, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20190245098
    Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.
    Type: Application
    Filed: December 13, 2016
    Publication date: August 8, 2019
    Inventors: Rahul RAMASWAMY, Hsu-Yu CHANG, Chia-Hong JAN, Walid M. HAFEZ, Neville L. DIAS, Roman W. OLAC-VAW, Chen-Guan LEE