Patents by Inventor Romel N. Manatad
Romel N. Manatad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230402350Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).Type: ApplicationFiled: August 24, 2023Publication date: December 14, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erwin Ian Vamenta ALMAGRO, Maria Clemens Ypil QUINONES, Romel N. MANATAD, Maria Cristina ESTACIO, Elsie Agdon CABAHUG
-
Patent number: 11791247Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).Type: GrantFiled: July 7, 2021Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erwin Ian Vamenta Almagro, Maria Clemens Ypil Quinones, Romel N. Manatad, Maria Cristina Estacio, Elsie Agdon Cabahug
-
Publication number: 20220238421Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.Type: ApplicationFiled: January 22, 2021Publication date: July 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Clemens Ypil QUINONES, Bigildis DOSDOS, Jerome TEYSSEYRE, Erwin Ian Vamenta ALMAGRO, Romel N. MANATAD
-
Publication number: 20220102248Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).Type: ApplicationFiled: July 7, 2021Publication date: March 31, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erwin Ian Vamenta ALMAGRO, Maria Clemens Ypil QUINONES, Romel N. MANATAD, Maria Cristina ESTACIO, Elsie Agdon CABAHUG
-
Publication number: 20210351099Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina ESTACIO, Elsie Agdon CABAHUG, Romel N. MANATAD
-
Patent number: 11088046Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.Type: GrantFiled: June 25, 2018Date of Patent: August 10, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina Estacio, Elsie Agdon Cabahug, Romel N. Manatad
-
Publication number: 20190393119Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina ESTACIO, Elsie Agdon CABAHUG, Romel N. MANATAD
-
Patent number: 9698143Abstract: In a general aspect, a wireless multichip module can include a leadframe structure with portions configured to receive at least one flip-chip mounted semiconductor die, including one or more of an integrated circuit, a high side MOSFET and/or a low side MOSFET, which can form a half-bridge circuit that is encapsulated in a molding compound. The module can be assembled without any bond wires (e.g., be wireless). The module may include carry passive components including an external input capacitor and/or an internal input capacitor.Type: GrantFiled: September 6, 2013Date of Patent: July 4, 2017Assignee: Fairchild Semiconductor CorporationInventors: Allan Tungul Flores, Romel N. Manatad
-
Publication number: 20140070329Abstract: A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor 150 or an internal input capacitor 350.Type: ApplicationFiled: September 6, 2013Publication date: March 13, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Allan Tungul Flores, Romel N. Manatad, Jan Vincent C. Mancelita
-
Publication number: 20140071650Abstract: A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor 150 or an internal input capacitor 350.Type: ApplicationFiled: September 6, 2013Publication date: March 13, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Allan Tungul Flores, Romel N. Manatad
-
Publication number: 20120168947Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: ApplicationFiled: February 24, 2012Publication date: July 5, 2012Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
-
Patent number: 8158506Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: GrantFiled: May 5, 2008Date of Patent: April 17, 2012Assignee: Fairchild Semiconductor CorporationInventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
-
Publication number: 20110244633Abstract: Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described.Type: ApplicationFiled: April 7, 2011Publication date: October 6, 2011Inventors: Ruben P. Madrid, Romel N. Manatad, Maria Clemens Y. Quinones
-
Patent number: 7906837Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.Type: GrantFiled: June 5, 2009Date of Patent: March 15, 2011Assignee: Fairchild Semiconductor CorporationInventors: Elsie Agdon Cabahug, Marvin Rosalejos Gestole, Margie Sebial Tumulak-Rios, Lilith U. Montayre, Romel N. Manatad
-
Patent number: 7816784Abstract: Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe.Type: GrantFiled: December 17, 2008Date of Patent: October 19, 2010Assignee: Fairchild Semiconductor CorporationInventors: Joon-Seo Son, Romel N. Manatad, Armand Vincent Jereza
-
Patent number: 7816178Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.Type: GrantFiled: July 9, 2009Date of Patent: October 19, 2010Assignee: Fairchild Semiconductor CorporationInventors: Ruben P. Madrid, Romel N. Manatad
-
Publication number: 20100164078Abstract: Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Ruben Madrid, Romel N. Manatad, Maria Clemens Y. Quinones
-
Publication number: 20100148328Abstract: Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more conductive layers disposed on a first surface of the substrate that electrically interconnect the semiconductor to one or more leads of the leadframe.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Joon-Seo Son, Romel N. Manatad, Armand Vincent Jereza
-
Publication number: 20090273082Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent Mancelita
-
Publication number: 20090269885Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.Type: ApplicationFiled: July 9, 2009Publication date: October 29, 2009Inventors: Ruben P. Madrid, Romel N. Manatad