Patents by Inventor Romeo Iacobut
Romeo Iacobut has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130044827Abstract: Provided is a communication protocol for communication via power line. For example, there is a power supply equipment for communication via a power line including a controller, a power line input coupled to the power line, and a current demodulator coupled to the power line input and the controller. The controller is configured to demodulate a first portion of a power signal of the power line at the power line input using the current demodulator and to receive a first bitstream over the power line. A second bitstream may be provided by the controller in order to modulate a voltage sent from the power supply equipment to a powered device via the power line. The powered device may further demodulate the modulated voltage to extract the second bitstream sent from the power supply equipment.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Applicant: BROADCOM CORPORATIONInventors: Marius Vladan, Stefan Van Roeyen, Steve Hoste, Jean-Francois Koleck, Luc D'haeze, Romeo Iacobut
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Patent number: 7550996Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.Type: GrantFiled: March 3, 2006Date of Patent: June 23, 2009Assignee: Easic CorporationInventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Levinthal, Richard Zeman
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Patent number: 7157937Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.Type: GrantFiled: July 22, 2005Date of Patent: January 2, 2007Assignee: eASIC CorporationInventors: Adrian Apostol, Petrica Avram, Romeo Iacobut, Adam Levinthal, Zvi Or-Bach, Ze′ev Wurman, Richard Zeman, Alon Kapel, George C. Grigore
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Patent number: 7105871Abstract: A semiconductor device may include a borderless logic array and area I/Os. The logic array may comprise a repeating core, and at least one of the area I/Os may be a configurable I/O. Furthermore, the configurable I/O may comprise at least one metal layer that is the same for all I/O configurations.Type: GrantFiled: December 9, 2003Date of Patent: September 12, 2006Assignee: eASIC CorporationInventors: Zvi Or-Bach, Laurence Cooke, Adrian Apostol, Romeo Iacobut
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Patent number: 7098691Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.Type: GrantFiled: July 27, 2004Date of Patent: August 29, 2006Assignee: eASIC CorporationInventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Leventhal, Richard Zeman
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Publication number: 20060164121Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.Type: ApplicationFiled: March 3, 2006Publication date: July 27, 2006Applicant: Easic CorporationInventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Levinthal, Richard Zeman
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Publication number: 20060028241Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.Type: ApplicationFiled: July 22, 2005Publication date: February 9, 2006Applicant: eASIC CorporationInventors: Adrian Apostol, Petrica Avram, Romeo Iacobut, Adam Levinthal, Zvi Or-Bach, Ze'ev Wurman, Richard Zeman, Alon Kapel, George Grigore
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Publication number: 20060022705Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.Type: ApplicationFiled: July 27, 2004Publication date: February 2, 2006Applicant: eASIC CorporationInventors: Zvi Or-Bach, Petrica Avram, Romeo Iacobut, Adrian Apostol, Ze'ev Wurman, Adam Leventhal, Richard Zeman
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Publication number: 20040161878Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.Type: ApplicationFiled: December 9, 2003Publication date: August 19, 2004Applicant: eASIC CorporationInventors: Zvi Or-Bach, Laurence Cooke, Adrian Apostol, Romeo Iacobut