Abstract: The present disclosure describes an optical system and method of operating the optical system. The optical system includes a substrate and first and second photonic integrated circuits. The first photonic integrated circuit is positioned on the substrate. The second photonic integrated circuit is positioned on the first photonic integrated circuit. The second photonic integrated circuit receives a first optical signal that includes a first mode and a second mode. The second photonic integrated circuit includes a polarization splitter rotator, a first demultiplexer, and a second demultiplexer. The polarization splitter rotator separates the first optical signal into a second optical with the first mode and a third optical signal with the first mode. The first and second demultiplexers separate the second and third optical signals into first and second pluralities of optical signals. The first and second pluralities of optical signals couple into the first photonic integrated circuit.

Abstract: Techniques for implementing a differential differencing TIA for coherent applications are disclosed.

Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.

Abstract: An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.

Abstract: A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.

Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.

Abstract: An apparatus comprises: a photodetector having a cathode and an anode to generate an output current; and a differential transimpedance amplifier (TIA) having a first amplifier input coupled to a first one of the cathode and the anode through a first AC coupling capacitor and a first feedforward resistor that is connected in parallel with the first AC coupling capacitor between the first one of the cathode and the anode and the first amplifier input, the differential TIA having a second amplifier input coupled to a second one of the cathode and the anode that is not the first one of the anode and the cathode, the differential TIA configured to convert the output current of the photodetector as presented at the first amplifier input and the second amplifier input to a differential output voltage.

Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.

Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.

Abstract: An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.

Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.

Abstract: An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.

Abstract: Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.

Abstract: Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.

Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.

Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.

Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.

Abstract: A multi-port coupled inductor with interference suppression is provided with a first signal port connected to a first resistor port via a first inductor; a second resistor port connected to the first resistor port via a second inductor; a second signal port connected to the second resistor port via a third inductor; a third resistor port connected to the first resistor port via a first resistor; a fourth resistor port connected to the third resistor port via a fourth inductor and to the second resistor port via a second resistor; a third signal port connected to the third resistor port via a fifth inductor; and a fourth signal port connected to the fourth resistor port via a sixth inductor.

Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.

Abstract: An apparatus includes a first digital-to-time converter (DTC) and a second DTC. The first DTC includes a sequence of delay stages. Each of the delay stages adds a delay to an input signal based on a control signal. Each delay stage includes a comparator and a capacitor coupled to an input of the comparator and to ground. The second DTC is coupled in parallel to the first DTC. The second DTC adds a delay to the input signal based on a complement of the control signal.