Abstract: A data processing system includes a number of processor cores each having a trace interface with an address signal carrying program addresses being executed, a processor core identification circuit connected to the trace interfaces and operable to replace a portion of some of the program addresses with a processor core identification that identifies which of the processor cores provided the program addresses, and an execution trace buffer operable to store the program addresses associated with non-sequential execution in the processor cores. At least some of the program addresses include the processor core identification along with address bits.

Abstract: A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Abstract: An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.

Abstract: A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Abstract: An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.

Abstract: A method and system for accessing and downloading data stored on a first mobile device by a second device over a cellular network is provided. First, a request is received from the second device for access to data on the first device. The request is then transmitted to the first mobile device and a communications link is established over the cellular network between the first mobile device to the second device. Access is provided to the second device to the data stored on the first mobile device. The data may also be downloaded from the first mobile device to the second device.