Abstract: A new read scheme is provided for an MRAM bit having a reference layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. The reference layer has a magnetization direction that is tilted with respect to an easy axis of the storage layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer.

Abstract: A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line having a first resistance is coupled to a first ferromagnetic layer and a second read line having a third resistance is coupled to a second ferromagnetic layer such that a voltage difference between the two read lines will produce a current flowing perpendicularly through each layer of the MTJ. A first write line having a second resistance is separated from the first read line by a first insulator and a second write line having a fourth resistance is separated from the second read line by a second insulator, and wherein the second and fourth resistances are lower than the first and third resistance.

Abstract: A pseudo-spin valve for memory applications, such as magnetoresistive random access memory (MRAM), and methods for fabricating the same, are disclosed. Advantageously, memory devices with the advantageous pseudo-spin valve configuration can be fabricated without cobalt-iron and without anti-ferromagnetic layers, thereby promoting switching repeatability.

Abstract: A magnetic memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive bit. The memory cells may each be coupled to a current driver. Each current driver may be inhibited so that it does not output a current. Inhibiting the output current prevents the memory from being written. By inhibiting some current drivers and not inhibiting other current drivers, the memory may be partitioned into read only and random access portions.

Abstract: A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be used to protect an entire row and/or column of MRAM bits. As a result, the MRAM bits are protected during a dose rate event.

Abstract: A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer.

Abstract: A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary bit values using less current than previous cell architectures. The improved memory cell may be used in a memory system with precision current drivers and auto-zero sense amplifiers in order to further lower power and improve overall system reliability.

Abstract: In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.

Abstract: A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Alternatively, a planar shield is affixed directly to a surface of semiconductor die containing an integrated circuit structure.

Abstract: A system and method for protecting MRAM bits during a dose rate event is described. A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be used to protect an entire row and/or column of MRAM bits.

Abstract: A current-perpendicular-to-plane (CPP) ring-shaped (RS) magnetoresistive random access memory (MRAM) element is provided in several embodiments including operational functionality of static read (SR) and dynamic read (DR). According to an embodiment, a memory element has one or more vias passing through a center hole in the CPP RS MRAM element. Each end of each via is coupled with a separate write line segment that extends radially from the center hole past a perimeter of the ring-shaped element. The write lines and vias are configured to generate magnetic fields for switching a magnetization direction of one or more layers of the ring-shaped bits in the array.

Abstract: A bias-adjusted giant magnetoresistive (GMR) device includes a ferromagnetic reference layer, which has a magnetization that remains relatively fixed when a range of magnetic fields is applied, and a ferromagnetic switching layer, which has a magnetization that can be changed by applying a relatively small magnetic field. In MRAM applications, the switching layer stores data in the form of the particular orientation of its magnetization relative to the magnetization of the reference layer. At least one of the reference and switching layers is split into at least two ferromagnetic layers separated by one or more layers of a nonmagnetic conductor, such that the hysteresis curve of resistance versus applied magnetic field is substantially symmetric about zero applied magnetic field.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells.

Abstract: A giant magnetoresistive memory device includes a magnetic sense layer, a magnetic storage layer, a non-magnetic spacer layer between the magnetic sense layer and the magnetic storage layer, and an antiferromagnetic layer formed in proximity to the magnetic storage layer. The antiferromagnetic layer couples magnetically in a controlled manner to the magnetic storage layer such that the magnetic storage layer has uniform and/or directional magnetization. Additionally or alternatively, an antiferromagnetic layer may be formed in proximity to the magnetic sense layer. The antiferromagnetic layer in proximity to the magnetic sense layer couples magnetically in a controlled manner to the magnetic sense layer such that the magnetic sense layer has uniform and/or directional magnetization.

Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.

Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.

Abstract: A magnetoresistive apparatus and method of operation with improved switching characteristics is provided. Switching of a magnetic direction of a magnetic layer of a magnetoresistive bit is promoted by parallel rotation of local magnetic direction of ends of the bit toward alignment with a hard-axis of the bit. Thus, an embodiment provides for expanded hard-axis magnetic volume of the bit ends to support hard-axis magnetization through bit shape alteration or doping, for example. A method provides for applying a hard-axis magnetic field to the bit ends for initiating switching and applying an easy-axis magnetic field for completing switching.

Abstract: A method and apparatus are presented for shifting a hysteresis loop of a magnetoresistive device. For example, a method provides for applying a bias current to a word line of the magnetoresistive device during either a read sequence or a write sequence. The bias current is preferably configured to substantially center a hysteresis loop of the device without switching a binary state of the device.

Abstract: The present invention provides for a tunneling magnetoresistive element and a method of reading a logical state of the element. An embodiment of the magnetoresistive element, for example, provides a tri-layer device having a storage layer, a sense layer and a barrier layer. The storage layer is a conducting, magnetic layer having a magnetization direction along an easy axis of the element. The storage layer is configured such that its magnetization direction will invert in response to an externally applied magnetic field of at least a first threshold strength. The binary state of the tunneling element is determinable from the magnetization direction of the storage layer. The sense layer is also a conducting, magnetic layer having a magnetization direction along the easy axis of the element. The sense layer is configured such that its magnetization direction will invert in response to an externally applied magnetic field of at least a second threshold strength.

Abstract: The present invention provides for a tunneling anisotropic magnetoresistive (TAM) device and a method of operation. An embodiment of the device provides for a magnetic conducting sense layer with a fixed edge spin and a center magnetization direction, a magnetic conducting storage layer with a fixed edge spin and a center magnetization direction, and a nonmagnetic nonconducting barrier layer sandwiched between the sense layer and the storage layer. In one embodiment, the two center magnetization directions are aligned with a hard axis of the device, and the center magnetization direction of the storage layer is indicative of a logical state of the device. A larger magnetic field is required to invert the center magnetization direction of the storage layer than is required to invert the center magnetization direction of the sense layer.