Patents by Inventor RON BAR-LEV
RON BAR-LEV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9917685Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: June 5, 2017Date of Patent: March 13, 2018Assignee: INTEL CORPORATIONInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20170279592Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: June 5, 2017Publication date: September 28, 2017Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 9673966Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: December 14, 2015Date of Patent: June 6, 2017Assignee: INTEL CORPORATIONInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20160211965Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: December 14, 2015Publication date: July 21, 2016Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 9215061Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: March 24, 2015Date of Patent: December 15, 2015Assignee: Intel CorporationInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20150200767Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: March 24, 2015Publication date: July 16, 2015Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 8989329Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: March 15, 2013Date of Patent: March 24, 2015Assignee: Intel CorporationInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Publication number: 20140270030Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN