Patents by Inventor Ron Bar-Or
Ron Bar-Or has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117386Abstract: A recombinant bacteria which is genetically modified to express formate dehydrogenase (FDH), phosphoribulokinase (prk) and Ribulose-Bisphosphate Carboxylase/oxygenase (RuBisCo) is disclosed. The bacteria may be modified to be autotrophic.Type: ApplicationFiled: October 22, 2020Publication date: April 11, 2024Applicant: Yeda Research and Development Co. Ltd.Inventors: Ron MILO, Shmuel GLEIZER, Niv ANTONOVSKY, Elad NOOR, Arren BAR-EVEN, Yehudit ZOHAR, Roee BEN NISSAN, Elad HERZ, Yinon Moise BAR-ON
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Patent number: 11687430Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.Type: GrantFiled: August 19, 2021Date of Patent: June 27, 2023Assignee: NXP USA, Inc.Inventors: Benny Michalovich, Ron Bar, Eran Glickman, Dmitriy Shurin
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Patent number: 11662324Abstract: A computer-based method for three-dimensional surface metrology of samples based on scanning electron microscopy and atomic force microscopy. The method includes: (i) using a scanning electron microscope (SEM) to obtain SEM data of a set of sites on a surface of a sample; (ii) using an atomic force microscope (AFM) to measure vertical parameters of sites in a calibration subset of the set; (iii) calibrating an algorithm, configured to estimate a vertical parameter of a site when SEM data of the site are fed as inputs, by determining free parameters of the algorithm, such that residuals between the algorithm-estimated vertical parameters and the AFM-measured vertical parameters are about minimized; and (iv) using the calibrated algorithm to estimate vertical parameters of the sites in the complement to the calibration subset.Type: GrantFiled: March 18, 2022Date of Patent: May 30, 2023Assignee: Applied Materials Israel Ltd.Inventors: Ido Almog, Ron Bar-Or, Lior Yaron
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Publication number: 20210397529Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.Type: ApplicationFiled: August 19, 2021Publication date: December 23, 2021Inventors: Benny Michalovich, Ron Bar, Eran Glickman, Dmitriy Shurin
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Patent number: 11126522Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.Type: GrantFiled: June 18, 2013Date of Patent: September 21, 2021Assignee: NXP USA, Inc.Inventors: Benny Michalovich, Ron Bar, Eran Glickman, Dmitriy Shurin
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Patent number: 10795797Abstract: A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto.Type: GrantFiled: November 25, 2011Date of Patent: October 6, 2020Assignee: NXP USA, Inc.Inventors: Eran Glickman, Ron Bar, Idan Ben Ami, Benny Michalovich
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Patent number: 10446434Abstract: According to an embodiment, a support module is provided for supporting a substrate. The support module may include a chuck and a vertical stage. The chuck may include multiple chuck segments that are independently movable. When the substrate is positioned on the chuck, different chuck segments are positioned under different areas of the substrate. The vertical stage may include multiple piezoelectric motors. Each piezoelectric motor may be configured to perform nanometric scale elevation and lowering movements. The multiple piezoelectric motors may be configured to independently move the multiple chuck segments.Type: GrantFiled: April 20, 2016Date of Patent: October 15, 2019Assignee: APPLIED MATERIALS ISRAEL LTD.Inventors: Doron Korngut, Yuri Belenky, Yoram Uziel, Ron Naftali, Ron Bar-or, Yuval Gronau
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Patent number: 10209762Abstract: A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (S1) of network elements at a first layer (L1) and a second set (S2) of one or more network elements at a second layer (L2). The network elements of the first set (S1) are configured for processing incoming data and the network elements of the second set (S2) of one or more network elements at the second layer (L2) are configured to process intermediate data received from the first set (S1) of network elements. The network elements of a particular subset (Si1) of the network elements of the first set (Si1) of network elements are connected to only a particular network element (Ei2) of the second set (S2) to transfer the incoming data processed by the network elements of the particular subset (Si1) to the particular network element (Ei2) of the second set (S2).Type: GrantFiled: September 27, 2013Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Eran Glickman, Ron Bar, Benny Michalovich
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Patent number: 9917685Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: June 5, 2017Date of Patent: March 13, 2018Assignee: INTEL CORPORATIONInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Patent number: 9835563Abstract: There may be provided an evaluation system that may include spatial sensors that include atomic force microscopes (AFMs) and a solid immersion lens. The AFMs are arranged to generate spatial relationship information that is indicative of a spatial relationship between the solid immersion lens and a substrate. The controller is arranged to receive the spatial relationship information and to send correction signals to the at least one location correction element for introducing a desired spatial relationship between the solid immersion lens and the substrate.Type: GrantFiled: November 19, 2015Date of Patent: December 5, 2017Assignee: APPLIED MATERIALS ISRAEL LTD.Inventors: Yoram Uziel, Ron Naftali, Ofer Adan, Haim Feldman, Ofer Shneyour, Ron Bar-Or, Doron Korngut
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Publication number: 20170309511Abstract: According to an embodiment, a support module is provided for supporting a substrate. The support module may include a chuck and a vertical stage. The chuck may include multiple chuck segments that are independently movable. When the substrate is positioned on the chuck, different chuck segments are positioned under different areas of the substrate. The vertical stage may include multiple piezoelectric motors. Each piezoelectric motor may be configured to perform nanometric scale elevation and lowering movements. The multiple piezoelectric motors may be configured to independently move the multiple chuck segments.Type: ApplicationFiled: April 20, 2016Publication date: October 26, 2017Inventors: Doron Korngut, Yuri Belenky, Yoram Uziel, Ron Naftali, Ron Bar-or, Yuval Gronau
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Patent number: 9780949Abstract: A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device against tampering is also described.Type: GrantFiled: July 24, 2013Date of Patent: October 3, 2017Assignee: NXP USA, INC.Inventors: Eran Glickman, Ron Bar, Benny Michalovich
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Publication number: 20170279592Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: June 5, 2017Publication date: September 28, 2017Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Patent number: 9678531Abstract: A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.Type: GrantFiled: February 14, 2014Date of Patent: June 13, 2017Assignee: NXP USA, INC.Inventors: Ron Bar, Evgeni Ginzburg, Eran Glickman
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Patent number: 9673966Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: GrantFiled: December 14, 2015Date of Patent: June 6, 2017Assignee: INTEL CORPORATIONInventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
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Patent number: 9626127Abstract: An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.Type: GrantFiled: July 21, 2010Date of Patent: April 18, 2017Assignee: NXP USA, INC.Inventors: Eran Glickman, Ron Bar, Benny Michalovich
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Publication number: 20160246358Abstract: A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (S1) of network elements at a first layer (L1) and a second set (S2) of one or more network elements at a second layer (L2). The network elements of the first set (S1) are configured for processing incoming data and the network elements of the second set (S2) of one or more network elements at the second layer (L2) are configured to process intermediate data received from the first set (S1) of network elements. The network elements of a particular subset (Si1) of the network elements of the first set (Si1) of network elements are connected to only a particular network element (Ei2) of the second set (S2) to transfer the incoming data processed by the network elements of the particular subset (Si1) to the particular network element (Ei2) of the second set (S2).Type: ApplicationFiled: September 27, 2013Publication date: August 25, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Eran GLICKMAN, Ron BAR, Benny MICHALOVICH
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Publication number: 20160211965Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.Type: ApplicationFiled: December 14, 2015Publication date: July 21, 2016Applicant: Intel CorporationInventors: DIMA HAMMAD, VADIM LEVIN, AMIR LAUFER, RON BAR-LEV, NOAM FAMILIA, ITAMAR LEVIN
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Publication number: 20160182229Abstract: A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device against tampering is also described.Type: ApplicationFiled: July 24, 2013Publication date: June 23, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Eran GLICKMAN, Ron BAR, Benny MICHALOVICH
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Publication number: 20160110275Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.Type: ApplicationFiled: June 18, 2013Publication date: April 21, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Benny MICHALOVICH, Ron BAR, Eran GLICKMAN, Dmitriy SHURIN