Abstract: A UE determines an activity status associated with each CC of a set of CCs based on PDCCH decoding of DCI. The set of CCs may be associated with hardware modules at the UE. An inactive set of CCs may be determined to have an inactive activity status. An active set of CCs may be determined to have an active activity status. The inactive set of CCs may be associated with a first set of hardware modules of the hardware modules. The active set of CCs may be associated with a second set of hardware modules of the hardware modules. The UE may activate a partial sleep mode at the first set of hardware modules associated with the inactive set of CCs.

Abstract: A method for communicating system activity in a communication system includes receiving communication beam activity information, the communication beam activity information related to communication information destined for a user device on a communication beam, the communication beam activity information comprising information relating to data activity on the communication beam, and using the communication beam activity information to determine a period within which the user device may enter an inactive state.

Abstract: A method for communicating system activity in a communication system includes receiving communication beam activity information, the communication beam activity information related to communication information destined for a user device on a communication beam, the communication beam activity information comprising information relating to data activity on the communication beam, and using the communication beam activity information to determine a period within which the user device may enter an inactive state.

Abstract: A multimode rake receiver comprise a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information encoded according to a second baseband modulation standard; and a common signal processing path, at least arranged to process in the first mode the first CDMA radio channel and in the second mode the second CDMA radio channel, wherein the common signal path comprises a common descrambling and de-spreading unit and a common hybrid code generating unit arranged to provide to the common descrambling and de-spreading unit chip codes applicable in the first mode to the first CDMA radio channel and in the second mode to the second CDMA radio channel.

Abstract: A multimode rake receiver comprise a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information encoded according to a second baseband modulation standard; and a common signal processing path, at least arranged to process in the first mode the first CDMA radio channel and in the second mode the second CDMA radio channel, wherein the common signal path comprises a common descrambling and de-spreading unit and a common hybrid code generating unit arranged to provide to the common descrambling and de-spreading unit chip codes applicable in the first mode to the first CDMA radio channel and in the second mode to the second CDMA radio channel.

Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information elemen

Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.

Abstract: A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.

Abstract: A receiver and a method for channel estimation, the method includes calculating at least one initial channel estimate; characterized by calculating an estimate of the channel based upon a mathematical relationship between a first group of pilot subcarriers and a second group of pilot subcarriers; whereas a difference between locations of pilot subcarriers of the first group and locations of corresponding pilot subcarriers of the second group is substantially constant; and at least one of the following conditions are fulfilled: (i) pilot subcarriers that belong to the same group of subcarriers are non-evenly spaced in a frequency domain, (ii) a pilot subcarrier of the first group and a corresponding pilot subcarrier of the second group are proximate to each other in the frequency domain.

Abstract: A method for locating an end of a received frame includes providing hypothetical trellis paths that end at different possible end points, performing a CRC check for each hypothetical trellis path, calculating a false detection variable for hypothetical trellis paths that passed the CRC check, and determining the end point of the received frame in response to the calculations.

Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.

Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element

Abstract: A pipelined device and method for executing transactions in a pipelined device, the method includes: setting limiter thresholds that define a maximal amount of pending transaction requests to be provided from one pipeline stage to another pipeline stage; executing an application while monitoring the performance of a device that comprises pipeline limiters; wherein the executing includes: selectively transferring transaction requests from one stage of the pipeline to another in response to the limiter thresholds, arbitrating between transaction requests at a certain pipeline stage, and executing selected transaction requests provided by the arbitrating.

Abstract: A device (100) for locating an end of a received frame, the device comprises: at least one memory unit (120) for storing path metrics; at least one processor, adapted to: provide hypothetical trellis paths that end at different possible end points; perform, for each hypothetical trellis path, a forward detection check; calculate a false detection variable for hypothetical trellis paths that passed the forward check; and determine the end point of the received frame in response to the calculations. Wherein the calculation of the forward detection check is much faster than the calculation of the false detection variable.

Abstract: A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.

Abstract: A receiver and a method for channel estimation, the method includes calculating at least one initial channel estimate; characterized by calculating an estimate of the channel based upon a mathematical relationship between a first group of pilot subcarriers and a second group of pilot subcarriers; whereas a difference between locations of pilot subcarriers of the first group and locations of corresponding pilot subcarriers of the second group is substantially constant; and at least one of the following conditions are fulfilled: (i) pilot subcarriers that belong to the same group of subcarriers are non-evenly spaced in a frequency domain, (ii) a pilot subcarrier of the first group and a corresponding pilot subcarrier of the second group are proximate to each other in the frequency domain.

Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.