Abstract: A multiprocessing system includes a plurality of data processing subsystems each coupled to an interprocessor communications bus through a corresponding interprocessor communications interface. The interprocessor communications interface corresponding to each data processing subsystem includes a receive FIFO buffer unit, a transmit FIFO buffer unit, and a control circuit. When a data processing subsystem desires to transfer data to another processing subsystem, the data processing subsystem packetizes the data in a variable word-length transfer packet which includes a header having a size field and a target field. The data processing subsystem causes the transfer packet to be stored within the transmit FIFO buffer unit. When a valid transmit packet is stored with the transmit FIFO buffer of the interprocessor communications interface corresponding to a particular processing subsystem, the associated control unit requests mastership of the interprocessor communications bus and transmit packet.