Patents by Inventor Ron Gabor

Ron Gabor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10802567
    Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
  • Patent number: 10776190
    Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
  • Publication number: 20200272474
    Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.
    Type: Application
    Filed: June 17, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Ron Gabor, Alaa Alameldeen, Abhishek Basak, Fangfei Liu, Francis McKeen, Joseph Nuzman, Carlos Rozas, Igor Yanover, Xiang Zou
  • Patent number: 10725755
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffrey J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Patent number: 10725788
    Abstract: A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jose Yallouz, Arkady Bramnik, Ron Gabor
  • Patent number: 10725849
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: David Durham, Siddhartha Chhabra, Kai Cong, Ron Gabor
  • Publication number: 20200201567
    Abstract: Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Ron Gabor, Tomer Stark, Joseph Nuzman, Ady Tal
  • Patent number: 10649783
    Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.
    Type: Grant
    Filed: April 30, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Patent number: 10585741
    Abstract: Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Tomer Stark, Ady Tal, Ron Gabor
  • Patent number: 10521361
    Abstract: Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Tomer Stark, Ron Gabor, Ady Tal, Joseph Nuzman
  • Publication number: 20190272214
    Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 5, 2019
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
  • Publication number: 20190235938
    Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 1, 2019
    Applicant: Intel Corporation
    Inventors: TOMER STARK, RON GABOR, JOSEPH NUZMAN
  • Publication number: 20190235948
    Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 1, 2019
    Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
  • Publication number: 20190227951
    Abstract: Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: David M. Durham, Ron Gabor
  • Patent number: 10346171
    Abstract: A processor of an aspect includes a plurality of physical storage locations, and a register rename unit. The register rename unit includes a first register rename storage structure that is to store a given physical storage location identifier, which is to identify a physical storage location of the plurality of physical storage locations, and that is to store a corresponding given one or more redundant bits. The register rename unit also includes a second register rename storage structure. The register rename unit also includes a first conductive path coupling the first and second register rename storage structures. The first conductive path is to convey the given one or more redundant bits end-to-end from the first register rename storage structure to the second register rename storage structure. Other processors are also disclosed, as well as methods and systems.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Ron Gabor, Yiannakis Sazeides, Arkady Bramnik
  • Patent number: 10324857
    Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Joseph Nuzman, Raanan Sade, Igor Yanover, Ron Gabor, Amit Gradstein
  • Patent number: 10319458
    Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Mohan J. Kumar, Theodros Yigzaw
  • Patent number: 10296416
    Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
  • Publication number: 20190108130
    Abstract: In one embodiment, a method includes: in response to a sub-cacheline memory access request, receiving a data-line from a memory coupled to a processor; receiving tag information included in metadata associated with the data-line from the memory; determining, in a memory controller, whether a first tag identifier of the tag information matches a tag portion of an address of the memory line associated with the sub-cacheline memory access request, and in response to determining a match, storing a first portion of the data-line associated with the first tag identifier in a cache line of a cache of the processor, the first portion a sub-cacheline width. This method allows data lines stored in memory associated with multiple different tag metadata to be divided into multiple cachelines comprising the sub-cacheline data associated with a particular metadata address tag. Other embodiments are described and claimed.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: David M. Durham, Ron Gabor, Rajat Agarwal
  • Publication number: 20190050283
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 27, 2018
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: David Durham, Siddhartha Chhabra, Kai Cong, Ron Gabor